From patchwork Tue Jun 9 10:45:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Lu X-Patchwork-Id: 211854 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 139E9C433DF for ; Tue, 9 Jun 2020 10:45:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DA2B5207C3 for ; Tue, 9 Jun 2020 10:45:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Ixbh/pRi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728758AbgFIKpo (ORCPT ); Tue, 9 Jun 2020 06:45:44 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:26511 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728305AbgFIKpm (ORCPT ); Tue, 9 Jun 2020 06:45:42 -0400 X-UUID: 3e298489a864435fb845463d1be7a578-20200609 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=eY5MvzczwNbrwtKhGEVAhCGRBXkqAd3J0N4ihq/a/Eg=; b=Ixbh/pRi2qVt4/u18b6/pZ6JYYn7wksjI/N+YKre+mLy3rJVXv/8QRu6uKffChwppnwMGrutMzgpt9fAKXVe76sjN8gLYTQ/x+U0h0q0x4v3wfgG3e91o3fKUHSAFWEFPuQXlCLLvR6KzoiGG/0RMVVOri53w8AHZQuzOxYQ7fc=; X-UUID: 3e298489a864435fb845463d1be7a578-20200609 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1802064524; Tue, 09 Jun 2020 18:45:37 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Jun 2020 18:45:36 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Jun 2020 18:45:34 +0800 From: Roger Lu To: Kevin Hilman , Rob Herring , Nicolas Boichat , Stephen Boyd CC: Fan Chen , HenryC Chen , YT Lee , Xiaoqing Liu , Charles Yang , Angus Lin , Mark Rutland , Matthias Brugger , Nishanth Menon , Roger Lu , , , , , Subject: [PATCH v9 1/4] dt-bindings: power: avs: add mtk svs dt-bindings Date: Tue, 9 Jun 2020 18:45:31 +0800 Message-ID: <20200609104534.29314-2-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200609104534.29314-1-roger.lu@mediatek.com> References: <20200609104534.29314-1-roger.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Document the binding for enabling mtk svs on MediaTek SoC. Signed-off-by: Roger Lu --- .../bindings/power/avs/mtk_svs.yaml | 141 ++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/avs/mtk_svs.yaml -- 2.18.0 diff --git a/Documentation/devicetree/bindings/power/avs/mtk_svs.yaml b/Documentation/devicetree/bindings/power/avs/mtk_svs.yaml new file mode 100644 index 000000000000..f16f4eb56ee3 --- /dev/null +++ b/Documentation/devicetree/bindings/power/avs/mtk_svs.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/avs/mtk_svs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Introduce SVS engine + +maintainers: + - Kevin Hilman + - Nishanth Menon + +description: |+ + The Smart Voltage Scaling(SVS) engine is a piece of hardware + which has several controllers(banks) for calculating suitable + voltage to different power domains(CPU/GPU/CCI) according to + chip process corner, temperatures and other factors. Then DVFS + driver could apply SVS bank voltage to PMIC/Buck. + +properties: + compatible: + const: mediatek,mt8183-svs + + reg: + description: Address range of the MTK SVS controller. + maxItems: 1 + + interrupts: + description: IRQ for the MTK SVS controller. + maxItems: 1 + + clocks: + description: Main clock for svs controller to work. + + clock-names: + const: main + + nvmem-cells: + maxItems: 2 + description: + Phandle to the calibration data provided by a nvmem device. + + nvmem-cell-names: + items: + - const: svs-calibration-data + - const: calibration-data + +patternProperties: + "^svs-(cpu-little|cpu-big|cci|gpu)$": + type: object + description: + Each subnode represents one SVS bank. + - svs-cpu-little (SVS bank device node of little CPU) + - svs-cpu-big (SVS bank device node of big CPU) + - svs-cci (SVS bank device node of CCI) + - svs-gpu (SVS bank device node of GPU) + + properties: + compatible: + enum: + - mediatek,mt8183-svs-cpu-little + - mediatek,mt8183-svs-cpu-big + - mediatek,mt8183-svs-cci + - mediatek,mt8183-svs-gpu + + power-domains: + description: Phandle to the associated power domain + maxItems: 1 + + operating-points-v2: true + + vcpu-little-supply: + description: PMIC buck of little CPU + + vcpu-big-supply: + description: PMIC buck of big CPU + + vcci-supply: + description: PMIC buck of CCI + + vgpu-spply: + description: PMIC buck of GPU + + required: + - compatible + - operating-points-v2 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + svs: svs@1100b000 { + compatible = "mediatek,mt8183-svs"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, <&thermal_calibration>; + nvmem-cell-names = "svs-calibration-data", "calibration-data"; + + svs_cpu_little: svs-cpu-little { + compatible = "mediatek,mt8183-svs-cpu-little"; + operating-points-v2 = <&cluster0_opp>; + vcpu-little-supply = <&mt6358_vproc12_reg>; + }; + + svs_cpu_big: svs-cpu-big { + compatible = "mediatek,mt8183-svs-cpu-big"; + operating-points-v2 = <&cluster1_opp>; + vcpu-big-supply = <&mt6358_vproc11_reg>; + }; + + svs_cci: svs-cci { + compatible = "mediatek,mt8183-svs-cci"; + operating-points-v2 = <&cci_opp>; + vcci-supply = <&mt6358_vproc12_reg>; + }; + + svs_gpu: svs-gpu { + compatible = "mediatek,mt8183-svs-gpu"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_2D>; + operating-points-v2 = <&gpu_opp_table>; + vgpu-spply = <&mt6358_vgpu_reg>; + }; + };