| Message ID | 20200427163238.1.Ib1faaabe236e37ea73be9b8dcc6aa034cb3c8804@changeid |
|---|---|
| State | New |
| Headers | show |
| Series | spi: pxa2xx: Apply CS clk quirk to BXT | expand |
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 73d2a65d0b6ef..20dcbd35611a7 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -150,6 +150,7 @@ static const struct lpss_config lpss_platforms[] = { .tx_threshold_hi = 48, .cs_sel_shift = 8, .cs_sel_mask = 3 << 8, + .cs_clk_stays_gated = true, }, { /* LPSS_CNL_SSP */ .offset = 0x200,
With a couple allies at Intel, and much badgering, I got confirmation from Intel that at least BXT suffers from the same SPI chip-select issue as Cannonlake (and beyond). The issue being that after going through runtime suspend/resume, toggling the chip-select line without also sending data does nothing. Add the quirk to BXT to briefly toggle dynamic clock gating off and on, forcing the fabric to wake up enough to notice the CS register change. Signed-off-by: Evan Green <evgreen@chromium.org> Cc: Shobhit Srivastava <shobhit.srivastava@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- I don't actually have a BXT (Broxton/Apollolake?) system to test this. To be honest I suspect the issue is there in older generations as well, but I couldn't get Intel to confirm that, so this seemed like the only safe change. --- drivers/spi/spi-pxa2xx.c | 1 + 1 file changed, 1 insertion(+)