@@ -80,6 +80,8 @@ enum {
MV_V2_PORT_CTRL = 0xf001,
MV_V2_PORT_CTRL_SWRST = BIT(15),
MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
+ MV_V2_PORT_MAC_TYPE_MASK = 0x7,
+ MV_V2_PORT_MAC_TYPE_RATE_MATCH = 0x6,
/* Temperature control/read registers (88X3310 only) */
MV_V2_TEMP_CTRL = 0xf08a,
MV_V2_TEMP_CTRL_MASK = 0xc000,
@@ -579,8 +581,24 @@ static int mv3310_aneg_done(struct phy_device *phydev)
return genphy_c45_aneg_done(phydev);
}
-static void mv3310_update_interface(struct phy_device *phydev)
+static int mv3310_update_interface(struct phy_device *phydev)
{
+ int val;
+
+ val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
+ if (val < 0)
+ return val;
+
+ /* In "XFI with Rate Matching" mode the PHY interface is fixed at
+ * 10Gb. The PHY adapts the rate to actual wire speed with help of
+ * internal 16KB buffer.
+ */
+ if ((val & MV_V2_PORT_MAC_TYPE_MASK) ==
+ MV_V2_PORT_MAC_TYPE_RATE_MATCH) {
+ phydev->interface = PHY_INTERFACE_MODE_10GBASER;
+ return 0;
+ }
+
if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
@@ -607,6 +625,8 @@ static void mv3310_update_interface(struct phy_device *phydev)
break;
}
}
+
+ return 0;
}
/* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
@@ -719,8 +739,11 @@ static int mv3310_read_status(struct phy_device *phydev)
if (err < 0)
return err;
- if (phydev->link)
- mv3310_update_interface(phydev);
+ if (phydev->link) {
+ err = mv3310_update_interface(phydev);
+ if (err < 0)
+ return err;
+ }
return 0;
}
When the hardware MACTYPE hardware configuration pins are set to "XFI with Rate Matching" the PHY interface operate at fixed 10Gbps speed. The MAC buffer packets in both directions to match various wire speeds. Read the MAC Type field in the Port Control register, and set the MAC interface speed accordingly. Signed-off-by: Baruch Siach <baruch@tkos.co.il> --- drivers/net/phy/marvell10g.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-)