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[203.254.224.24]) by mx.google.com with ESMTPS id zi8si6632254pac.40.2013.12.09.00.49.14 for (version=TLSv1 cipher=RC4-MD5 bits=128/128); Mon, 09 Dec 2013 00:49:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MXJ00C357606LD0@mailout1.samsung.com>; Mon, 09 Dec 2013 17:49:12 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 30.84.15154.70485A25; Mon, 09 Dec 2013 17:49:12 +0900 (KST) X-AuditID: cbfee68e-b7fee6d000003b32-bc-52a584070f9a Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id EA.69.17171.70485A25; Mon, 09 Dec 2013 17:49:11 +0900 (KST) Received: from localhost.localdomain.com ([107.108.73.95]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MXJ00KEY75NNA30@mmp1.samsung.com>; Mon, 09 Dec 2013 17:49:11 +0900 (KST) From: Rajeshwari S Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, u-boot-review@google.com, alim.akhtar@samsung.com, trini@ti.com Subject: [PATCH 04/11 V10] EXYNOS5420: Add dmc and phy_control register structure Date: Mon, 09 Dec 2013 14:20:40 +0530 Message-id: <1386579047-2501-5-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.11.7 In-reply-to: <1386579047-2501-1-git-send-email-rajeshwari.s@samsung.com> References: <1386579047-2501-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrLLMWRmVeSWpSXmKPExsWyRsSkSpejZWmQwfxt+hYP5m1js3i4/iaL RceRFkaLKYe/sFh827KN0WLy4vnMFstfb2S3eLu3k92Bw2N2w0UWjwWbSj3uXNvD5nH2zg5G j74tqxg9jt/YzhTAFsVlk5Kak1mWWqRvl8CVcWvqBtaCN1oVz7+UNjBuUO5i5OCQEDCRWP+F v4uRE8gUk7hwbz0biC0ksJRR4uCuJIi4icS6A7NYuhi5gOKLGCUavu5lhHC6mCRO7XrBDDKI Dahq44kEkAYRAQmJX/1XwWqYBeYzSiz/vZsZJCEsECyxe94asA0sAqoSL29NZQexeQXcJT4u e8YEsU1RYsaSZ4wgNqeAh8TF6R9YIC5yl7j7p4MVomYdu8SHJYwQcwQkvk0+xALxjKzEpgPM ECWSEgdX3GCZwCi8gJFhFaNoakFyQXFSepGRXnFibnFpXrpecn7uJkZg0J/+96xvB+PNA9aH GJOBxk1klhJNzgdGTV5JvKGxmZGFqYmpsZG5pRlpwkrivIseJgUJCaQnlqRmp6YWpBbFF5Xm pBYfYmTi4JRqYGTbX3ApdY7NXq45ih0ObppH4/lOMm1desSSQb3xwf8FqmtblVO03Apmnpyc c2d7ZVKdsaVA4zHWWwfEi9YcTo7b/rS+VWPnyoAfT0+laO710psiVGZS4yn32/nq0oqnvOce eB29pfrj0LnpfDMrUmSqpi8tWfzyh8g1i5r7l68fqpzJc3Bbtr0SS3FGoqEWc1FxIgBA93Lk kAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLIsWRmVeSWpSXmKPExsVy+t9jAV32lqVBBscPWFk8mLeNzeLh+pss Fh1HWhgtphz+wmLxbcs2RovJi+czWyx/vZHd4u3eTnYHDo/ZDRdZPBZsKvW4c20Pm8fZOzsY Pfq2rGL0OH5jO1MAW1QDo01GamJKapFCal5yfkpmXrqtkndwvHO8qZmBoa6hpYW5kkJeYm6q rZKLT4CuW2YO0EVKCmWJOaVAoYDE4mIlfTtME0JD3HQtYBojdH1DguB6jAzQQMIaxoxbUzew FrzRqnj+pbSBcYNyFyMnh4SAicS6A7NYIGwxiQv31rN1MXJxCAksYpRo+LqXEcLpYpI4tesF cxcjBwcbUMfGEwkgDSICEhK/+q+C1TALzGeUWP57NzNIQlggWGL3vDVsIDaLgKrEy1tT2UFs XgF3iY/LnjFBbFOUmLHkGSOIzSngIXFx+gewK4SAau7+6WCdwMi7gJFhFaNoakFyQXFSeq6h XnFibnFpXrpecn7uJkZwZD2T2sG4ssHiEKMAB6MSD+8K1qVBQqyJZcWVuYcYJTiYlUR4zWuA QrwpiZVVqUX58UWlOanFhxiTga6ayCwlmpwPjPq8knhDYxNzU2NTSxMLEzNL0oSVxHkPtFoH CgmkJ5akZqemFqQWwWxh4uCUamDsbGs+uvts3KlLfzeGVv3WCXHmE85men/OfM7DrbGVLd4H P2YLaBoWLWBrW8/wXDbkyScjs61Zp1K1UtVD/sVenc3b07SCk+mbksVVvlkRMeb5qv3fuoyj XDW1jRtu/GfnOOCz0SOIt3Xb9FNvOuXeXTn1ZnL8LN+Xcg5Fh3d8Oq4TtpolcJ8SS3FGoqEW c1FxIgAg+spS8AIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rajeshwari.s@samsung.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.169 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add dmc and phy_control register structure for 5420. Signed-off-by: Rajeshwari S Shinde --- Changes in V10: - New patch arch/arm/include/asm/arch-exynos/dmc.h | 167 +++++++++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index f65c676..32ad3ae 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -205,6 +205,127 @@ struct exynos5_dmc { unsigned int pmcnt3_ppc_a; }; +struct exynos5420_dmc { + unsigned int concontrol; + unsigned int memcontrol; + unsigned int cgcontrol; + unsigned char res500[0x4]; + unsigned int directcmd; + unsigned int prechconfig0; + unsigned int phycontrol0; + unsigned int prechconfig1; + unsigned char res1[0x8]; + unsigned int pwrdnconfig; + unsigned int timingpzq; + unsigned int timingref; + unsigned int timingrow0; + unsigned int timingdata0; + unsigned int timingpower0; + unsigned int phystatus; + unsigned int etctiming; + unsigned int chipstatus; + unsigned char res3[0x8]; + unsigned int mrstatus; + unsigned char res4[0x8]; + unsigned int qoscontrol0; + unsigned char resr5[0x4]; + unsigned int qoscontrol1; + unsigned char res6[0x4]; + unsigned int qoscontrol2; + unsigned char res7[0x4]; + unsigned int qoscontrol3; + unsigned char res8[0x4]; + unsigned int qoscontrol4; + unsigned char res9[0x4]; + unsigned int qoscontrol5; + unsigned char res10[0x4]; + unsigned int qoscontrol6; + unsigned char res11[0x4]; + unsigned int qoscontrol7; + unsigned char res12[0x4]; + unsigned int qoscontrol8; + unsigned char res13[0x4]; + unsigned int qoscontrol9; + unsigned char res14[0x4]; + unsigned int qoscontrol10; + unsigned char res15[0x4]; + unsigned int qoscontrol11; + unsigned char res16[0x4]; + unsigned int qoscontrol12; + unsigned char res17[0x4]; + unsigned int qoscontrol13; + unsigned char res18[0x4]; + unsigned int qoscontrol14; + unsigned char res19[0x4]; + unsigned int qoscontrol15; + unsigned char res20[0x4]; + unsigned int timing_set_sw; + unsigned int timingrow1; + unsigned int timingdata1; + unsigned int timingpower1; + unsigned char res300[0x4]; + unsigned int wrtra_config; + unsigned int rdlvl_config; + unsigned char res21[0x4]; + unsigned int brbrsvcontrol; + unsigned int brbrsvconfig; + unsigned int brbqosconfig; + unsigned char res301[0x14]; + unsigned int wrlvl_config0; + unsigned int wrlvl_config1; + unsigned int wrlvl_status; + unsigned char res23[0x4]; + unsigned int ppcclockon; + unsigned int perevconfig0; + unsigned int perevconfig1; + unsigned int perevconfig2; + unsigned int perevconfig3; + unsigned char res24[0xc]; + unsigned int control_io_rdata; + unsigned char res240[0xc]; + unsigned int cacal_config0; + unsigned int cacal_config1; + unsigned int cacal_status; + unsigned char res302[0xa4]; + unsigned int bp_control0; + unsigned int bp_config0_r; + unsigned int bp_config0_w; + unsigned char res303[0x4]; + unsigned int bp_control1; + unsigned int bp_config1_r; + unsigned int bp_config1_w; + unsigned char res304[0x4]; + unsigned int bp_control2; + unsigned int bp_config2_r; + unsigned int bp_config2_w; + unsigned char res305[0x4]; + unsigned int bp_control3; + unsigned int bp_config3_r; + unsigned int bp_config3_w; + unsigned char res306[0xddb4]; + unsigned int pmnc_ppc; + unsigned char res25[0xc]; + unsigned int cntens_ppc; + unsigned char res26[0xc]; + unsigned int cntenc_ppc; + unsigned char res27[0xc]; + unsigned int intens_ppc; + unsigned char res28[0xc]; + unsigned int intenc_ppc; + unsigned char res29[0xc]; + unsigned int flag_ppc; + unsigned char res30[0xac]; + unsigned int ccnt_ppc; + unsigned char res31[0xc]; + unsigned int pmcnt0_ppc; + unsigned char res32[0xc]; + unsigned int pmcnt1_ppc; + unsigned char res33[0xc]; + unsigned int pmcnt2_ppc; + unsigned char res34[0xc]; + unsigned int pmcnt3_ppc; +}; + struct exynos5_phy_control { unsigned int phy_con0; unsigned int phy_con1; @@ -252,6 +373,52 @@ struct exynos5_phy_control { unsigned int phy_con42; }; +struct exynos5420_phy_control { + unsigned int phy_con0; + unsigned int phy_con1; + unsigned int phy_con2; + unsigned int phy_con3; + unsigned int phy_con4; + unsigned int phy_con5; + unsigned int phy_con6; + unsigned char res2[0x4]; + unsigned int phy_con8; + unsigned char res5[0x4]; + unsigned int phy_con10; + unsigned int phy_con11; + unsigned int phy_con12; + unsigned int phy_con13; + unsigned int phy_con14; + unsigned int phy_con15; + unsigned int phy_con16; + unsigned char res4[0x4]; + unsigned int phy_con17; + unsigned int phy_con18; + unsigned int phy_con19; + unsigned int phy_con20; + unsigned int phy_con21; + unsigned int phy_con22; + unsigned int phy_con23; + unsigned int phy_con24; + unsigned int phy_con25; + unsigned int phy_con26; + unsigned int phy_con27; + unsigned int phy_con28; + unsigned int phy_con29; + unsigned int phy_con30; + unsigned int phy_con31; + unsigned int phy_con32; + unsigned int phy_con33; + unsigned int phy_con34; + unsigned char res6[0x8]; + unsigned int phy_con37; + unsigned char res7[0x4]; + unsigned int phy_con39; + unsigned int phy_con40; + unsigned int phy_con41; + unsigned int phy_con42; +}; + enum ddr_mode { DDR_MODE_DDR2, DDR_MODE_DDR3,