diff mbox series

[tip:,perf/core] perf/x86/intel: Add more available bits for OFFCORE_RESPONSE of Intel Tremont

Message ID 158991385175.17951.3596220331125126731.tip-bot2@tip-bot2
State New
Headers show
Series [tip:,perf/core] perf/x86/intel: Add more available bits for OFFCORE_RESPONSE of Intel Tremont | expand

Commit Message

thermal-bot for Julien Panis May 19, 2020, 6:44 p.m. UTC 
The following commit has been merged into the perf/core branch of tip:

Commit-ID:     0813c40556fce1eeefb996e020cc5339e0b84137
Gitweb:        https://git.kernel.org/tip/0813c40556fce1eeefb996e020cc5339e0b84137
Author:        Kan Liang <kan.liang@linux.intel.com>
AuthorDate:    Fri, 01 May 2020 05:54:42 -07:00
Committer:     Peter Zijlstra <peterz@infradead.org>
CommitterDate: Tue, 19 May 2020 20:34:16 +02:00

perf/x86/intel: Add more available bits for OFFCORE_RESPONSE of Intel Tremont

The mask in the extra_regs for Intel Tremont need to be extended to
allow more defined bits.

"Outstanding Requests" (bit 63) is only available on MSR_OFFCORE_RSP0;

Fixes: 6daeb8737f8a ("perf/x86/intel: Add Tremont core PMU support")
Reported-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20200501125442.7030-1-kan.liang@linux.intel.com
---
 arch/x86/events/intel/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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Patch

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 332954c..ca35c8b 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -1892,8 +1892,8 @@  static __initconst const u64 tnt_hw_cache_extra_regs
 
 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
 	/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
-	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffffff9fffull, RSP_0),
-	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xffffff9fffull, RSP_1),
+	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
+	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
 	EVENT_EXTRA_END
 };