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[203.254.224.34]) by mx.google.com with ESMTPS id sw1si4805099pbc.12.2013.12.20.01.33.13 for (version=TLSv1 cipher=RC4-MD5 bits=128/128); Fri, 20 Dec 2013 01:33:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MY300BVYMJBJ0C0@mailout4.samsung.com>; Fri, 20 Dec 2013 18:33:11 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.124]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id B6.33.10364.7DE04B25; Fri, 20 Dec 2013 18:33:11 +0900 (KST) X-AuditID: cbfee690-b7f266d00000287c-d6-52b40ed75e01 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 5B.94.29263.7DE04B25; Fri, 20 Dec 2013 18:33:11 +0900 (KST) Received: from localhost.localdomain.com ([107.108.73.95]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MY300LCIMIYHJ70@mmp1.samsung.com>; Fri, 20 Dec 2013 18:33:10 +0900 (KST) From: Rajeshwari S Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, u-boot-review@google.com, alim.akhtar@samsung.com Subject: [PATCH 04/11 V12] EXYNOS5420: Add dmc and phy_control register structure Date: Fri, 20 Dec 2013 15:04:33 +0530 Message-id: <1387532080-9131-5-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.11.7 In-reply-to: <1387532080-9131-1-git-send-email-rajeshwari.s@samsung.com> References: <1387532080-9131-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKLMWRmVeSWpSXmKPExsWyRsSkRvc635Ygg1uvVC0ezNvGZvFw/U0W i44jLYwWUw5/YbH4tmUbo8Xy1xvZLd7u7WR3YPeY3XCRxWPBplKPO9f2sHmcvbOD0aNvyyrG ANYoLpuU1JzMstQifbsEroy3D6cyFpzSrlizzKWB8adyFyMnh4SAicTRzQ8ZIWwxiQv31rN1 MXJxCAksZZT4dOw/cxcjB1hR8zQDiPgiRolj/YtYIZwuJokbizqYQIrYgIo2nkgAGSQiICHx q/8qI0gNs0A/o8TH3f9ZQRLCAsESf6f/YAGxWQRUJbYs3QS2mVfAXeJF2wyoKxQlZix5BmZz CnhIHN72lA3EFgKqWTJrMgvIUAmBeewSnV8+QA0SkPg2+RALxKWyEpsOMEPMkZQ4uOIGywRG 4QWMDKsYRVMLkguKk9KLTPSKE3OLS/PS9ZLzczcxAoP89L9nE3Yw3jtgfYgxGWjcRGYp0eR8 YJTklcQbGpsZWZiamBobmVuakSasJM6r9igpSEggPbEkNTs1tSC1KL6oNCe1+BAjEwenVANj 1Y+V/r4MESeePL9bk/B/2fpLvZ8e1FoFMK06ZcbxN1DPf4Wzb7h7drfsar+/d7YGmIX/eJY7 deOq+4xOVpma9z2zm+z3idcdULrIxyOQphtfMt07LMDH/G9veI7v3MlSj7ssNV1En8c8f5DP eNHvvebO/NRCgZXCM2ayBy9Y6mFoaaG9qUaJpTgj0VCLuag4EQBxJnxFiAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrEIsWRmVeSWpSXmKPExsVy+t9jAd3rfFuCDKY1yVg8mLeNzeLh+pss Fh1HWhgtphz+wmLxbcs2RovlrzeyW7zd28nuwO4xu+Eii8eCTaUed67tYfM4e2cHo0ffllWM AaxRDYw2GamJKalFCql5yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUB3 KCmUJeaUAoUCEouLlfTtME0IDXHTtYBpjND1DQmC6zEyQAMJaxgz3j6cylhwSrtizTKXBsaf yl2MHBwSAiYSzdMMuhg5gUwxiQv31rN1MXJxCAksYpQ41r+IFcLpYpK4saiDCaSBDahh44kE kAYRAQmJX/1XGUFqmAX6GSU+7v7PCpIQFgiW+Dv9BwuIzSKgKrFl6SZGEJtXwF3iRdsMRoht ihIzljwDszkFPCQOb3vKBmILAdUsmTWZZQIj7wJGhlWMoqkFyQXFSem5hnrFibnFpXnpesn5 uZsYwTH0TGoH48oGi0OMAhyMSjy8Dbabg4RYE8uKK3MPMUpwMCuJ8HI8BwrxpiRWVqUW5ccX leakFh9iTAa6aiKzlGhyPjC+80riDY1NzE2NTS1NLEzMLEkTVhLnPdBqHSgkkJ5YkpqdmlqQ WgSzhYmDU6qB0e6kf4bKBIXsyVF2PPs2b6rMjPbZu3bDn82XzjKdvmHgIXtbq8Mpqv5JWHit za/rSgW36y5wcb2WjPSv6jfhtKw8vOPvv4zWkHXXooXiEi22nQz7Mq3R7+rm60cc2LJ2t75n 4Hac9tPGrZmxr/TGvP0h4msmxepczZkUv+z22pUKH2aIdTRHK7EUZyQaajEXFScCAKTZRRDl AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Removed-Original-Auth: Dkim didn't pass. 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Signed-off-by: Rajeshwari S Shinde Acked-by: Simon Glass --- Changes in V10: - New patch Changes in V11: - None Changes in V12: - None arch/arm/include/asm/arch-exynos/dmc.h | 167 +++++++++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index f65c676..32ad3ae 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -205,6 +205,127 @@ struct exynos5_dmc { unsigned int pmcnt3_ppc_a; }; +struct exynos5420_dmc { + unsigned int concontrol; + unsigned int memcontrol; + unsigned int cgcontrol; + unsigned char res500[0x4]; + unsigned int directcmd; + unsigned int prechconfig0; + unsigned int phycontrol0; + unsigned int prechconfig1; + unsigned char res1[0x8]; + unsigned int pwrdnconfig; + unsigned int timingpzq; + unsigned int timingref; + unsigned int timingrow0; + unsigned int timingdata0; + unsigned int timingpower0; + unsigned int phystatus; + unsigned int etctiming; + unsigned int chipstatus; + unsigned char res3[0x8]; + unsigned int mrstatus; + unsigned char res4[0x8]; + unsigned int qoscontrol0; + unsigned char resr5[0x4]; + unsigned int qoscontrol1; + unsigned char res6[0x4]; + unsigned int qoscontrol2; + unsigned char res7[0x4]; + unsigned int qoscontrol3; + unsigned char res8[0x4]; + unsigned int qoscontrol4; + unsigned char res9[0x4]; + unsigned int qoscontrol5; + unsigned char res10[0x4]; + unsigned int qoscontrol6; + unsigned char res11[0x4]; + unsigned int qoscontrol7; + unsigned char res12[0x4]; + unsigned int qoscontrol8; + unsigned char res13[0x4]; + unsigned int qoscontrol9; + unsigned char res14[0x4]; + unsigned int qoscontrol10; + unsigned char res15[0x4]; + unsigned int qoscontrol11; + unsigned char res16[0x4]; + unsigned int qoscontrol12; + unsigned char res17[0x4]; + unsigned int qoscontrol13; + unsigned char res18[0x4]; + unsigned int qoscontrol14; + unsigned char res19[0x4]; + unsigned int qoscontrol15; + unsigned char res20[0x4]; + unsigned int timing_set_sw; + unsigned int timingrow1; + unsigned int timingdata1; + unsigned int timingpower1; + unsigned char res300[0x4]; + unsigned int wrtra_config; + unsigned int rdlvl_config; + unsigned char res21[0x4]; + unsigned int brbrsvcontrol; + unsigned int brbrsvconfig; + unsigned int brbqosconfig; + unsigned char res301[0x14]; + unsigned int wrlvl_config0; + unsigned int wrlvl_config1; + unsigned int wrlvl_status; + unsigned char res23[0x4]; + unsigned int ppcclockon; + unsigned int perevconfig0; + unsigned int perevconfig1; + unsigned int perevconfig2; + unsigned int perevconfig3; + unsigned char res24[0xc]; + unsigned int control_io_rdata; + unsigned char res240[0xc]; + unsigned int cacal_config0; + unsigned int cacal_config1; + unsigned int cacal_status; + unsigned char res302[0xa4]; + unsigned int bp_control0; + unsigned int bp_config0_r; + unsigned int bp_config0_w; + unsigned char res303[0x4]; + unsigned int bp_control1; + unsigned int bp_config1_r; + unsigned int bp_config1_w; + unsigned char res304[0x4]; + unsigned int bp_control2; + unsigned int bp_config2_r; + unsigned int bp_config2_w; + unsigned char res305[0x4]; + unsigned int bp_control3; + unsigned int bp_config3_r; + unsigned int bp_config3_w; + unsigned char res306[0xddb4]; + unsigned int pmnc_ppc; + unsigned char res25[0xc]; + unsigned int cntens_ppc; + unsigned char res26[0xc]; + unsigned int cntenc_ppc; + unsigned char res27[0xc]; + unsigned int intens_ppc; + unsigned char res28[0xc]; + unsigned int intenc_ppc; + unsigned char res29[0xc]; + unsigned int flag_ppc; + unsigned char res30[0xac]; + unsigned int ccnt_ppc; + unsigned char res31[0xc]; + unsigned int pmcnt0_ppc; + unsigned char res32[0xc]; + unsigned int pmcnt1_ppc; + unsigned char res33[0xc]; + unsigned int pmcnt2_ppc; + unsigned char res34[0xc]; + unsigned int pmcnt3_ppc; +}; + struct exynos5_phy_control { unsigned int phy_con0; unsigned int phy_con1; @@ -252,6 +373,52 @@ struct exynos5_phy_control { unsigned int phy_con42; }; +struct exynos5420_phy_control { + unsigned int phy_con0; + unsigned int phy_con1; + unsigned int phy_con2; + unsigned int phy_con3; + unsigned int phy_con4; + unsigned int phy_con5; + unsigned int phy_con6; + unsigned char res2[0x4]; + unsigned int phy_con8; + unsigned char res5[0x4]; + unsigned int phy_con10; + unsigned int phy_con11; + unsigned int phy_con12; + unsigned int phy_con13; + unsigned int phy_con14; + unsigned int phy_con15; + unsigned int phy_con16; + unsigned char res4[0x4]; + unsigned int phy_con17; + unsigned int phy_con18; + unsigned int phy_con19; + unsigned int phy_con20; + unsigned int phy_con21; + unsigned int phy_con22; + unsigned int phy_con23; + unsigned int phy_con24; + unsigned int phy_con25; + unsigned int phy_con26; + unsigned int phy_con27; + unsigned int phy_con28; + unsigned int phy_con29; + unsigned int phy_con30; + unsigned int phy_con31; + unsigned int phy_con32; + unsigned int phy_con33; + unsigned int phy_con34; + unsigned char res6[0x8]; + unsigned int phy_con37; + unsigned char res7[0x4]; + unsigned int phy_con39; + unsigned int phy_con40; + unsigned int phy_con41; + unsigned int phy_con42; +}; + enum ddr_mode { DDR_MODE_DDR2, DDR_MODE_DDR3,