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[203.254.224.25]) by mx.google.com with ESMTPS id pi8si4766273pac.175.2013.12.20.01.33.17 for (version=TLSv1 cipher=RC4-MD5 bits=128/128); Fri, 20 Dec 2013 01:33:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MY3001F5MJG3TD0@mailout2.samsung.com>; Fri, 20 Dec 2013 18:33:16 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.124]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id AA.3B.10092.BDE04B25; Fri, 20 Dec 2013 18:33:16 +0900 (KST) X-AuditID: cbfee68f-b7f156d00000276c-93-52b40edb88a5 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id FC.94.29263.BDE04B25; Fri, 20 Dec 2013 18:33:15 +0900 (KST) Received: from localhost.localdomain.com ([107.108.73.95]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MY300LCIMIYHJ70@mmp1.samsung.com>; Fri, 20 Dec 2013 18:33:15 +0900 (KST) From: Rajeshwari S Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, u-boot-review@google.com, alim.akhtar@samsung.com Subject: [PATCH 07/11 V12] Exynos5420: Add support for 5420 in pinmux and gpio Date: Fri, 20 Dec 2013 15:04:36 +0530 Message-id: <1387532080-9131-8-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.11.7 In-reply-to: <1387532080-9131-1-git-send-email-rajeshwari.s@samsung.com> References: <1387532080-9131-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrCLMWRmVeSWpSXmKPExsWyRsSkRvcO35Ygg4M+Fg/mbWOzeLj+JotF x5EWRosph7+wWHzbso3RYvnrjewWb/d2sjuwe8xuuMjisWBTqceda3vYPM7e2cHo0bdlFWMA axSXTUpqTmZZapG+XQJXxuWtu1kL5lZVLL/6irWBcU1yFyMHh4SAicT+065djJxAppjEhXvr 2boYuTiEBJYySnyc8p8VImEicWfzSqjEIkaJDwv2sUA4XUwSPW9aGUEmsQFVbTyRANIgIiAh 8av/KiNIDbNAP9Ck3RCThAX8JJr+XGcEsVkEVCW6/q5gB+nlFXCXeP5ZBGKZosSMJc/ASjgF PCQOb3vKBmILAZUsmTUZbK+EwDx2iVV7u9gg5ghIfJt8iAXiG1mJTQeYIeZIShxccYNlAqPw AkaGVYyiqQXJBcVJ6UXGesWJucWleel6yfm5mxiBIX7637P+HYx3D1gfYkwGGjeRWUo0OR8Y I3kl8YbGZkYWpiamxkbmlmakCSuJ895/mBQkJJCeWJKanZpakFoUX1Sak1p8iJGJg1OqgTF+ 0ZOpzLwGjE87r+b05Gz1Zte5U33k/2cDCTPPLX2a89ueHjWwNOiePWHVoYsbpv72C+hQWs79 Senx/nm8DNICyldPtMRVtrdt7ywOaOCKKNuZz87tN9fC7Ghxx4xCp8ZsIxb1S7+Sn3bsi3Q1 2rng6MUZQfU2W8UKdp3df/Inc8nu2auiGZVYijMSDbWYi4oTARh2ULuHAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMIsWRmVeSWpSXmKPExsVy+t9jAd3bfFuCDJbuMbR4MG8bm8XD9TdZ LDqOtDBaTDn8hcXi25ZtjBbLX29kt3i7t5Pdgd1jdsNFFo8Fm0o97lzbw+Zx9s4ORo++LasY A1ijGhhtMlITU1KLFFLzkvNTMvPSbZW8g+Od403NDAx1DS0tzJUU8hJzU22VXHwCdN0yc4Du UFIoS8wpBQoFJBYXK+nbYZoQGuKmawHTGKHrGxIE12NkgAYS1jBmXN66m7VgblXF8quvWBsY 1yR3MXJySAiYSNzZvJINwhaTuHBvPZDNxSEksIhR4sOCfSwQTheTRM+bVsYuRg4ONqCOjScS QBpEBCQkfvVfZQSpYRboZ5T4uPs/K0hCWMBPounPdUYQm0VAVaLr7wp2kF5eAXeJ559FIJYp SsxY8gyshFPAQ+LwtqdgRwgBlSyZNZllAiPvAkaGVYyiqQXJBcVJ6bmGesWJucWleel6yfm5 mxjBUfRMagfjygaLQ4wCHIxKPLwNtpuDhFgTy4orcw8xSnAwK4nwcjwHCvGmJFZWpRblxxeV 5qQWH2JMBjpqIrOUaHI+MMLzSuINjU3MTY1NLU0sTMwsSRNWEuc90GodKCSQnliSmp2aWpBa BLOFiYNTqoExnrM28+6a3icykhf+PNj2j3mHpLVtW8VKpeD/HQ/z9zOVbphUOslcd/O/a5b3 L/+Qn9Hw443R1/2GElbvlKfzas9ed8ZjaqP4JQHW9OZm76Nbt31mYJZ/U310YpFkShSz+vuO vIioq4+Pz9hUXa62RkLzxm2jV+VP5/J8e/t1nbJWv8FGBUU/JZbijERDLeai4kQA7T+D/OYC AAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rajeshwari.s@samsung.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.52 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Adds code in pinmux and gpio framework to support Exynos5420. Signed-off-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Saraswat Signed-off-by: Rajeshwari S Shinde Acked-by: Simon Glass --- Changes in V2: - None Changes in V3: - None Changes in V4: - Added correct calculation of gpio based addresses. Changes in V5: - None Changes in V6: - None Changes in V7: - Corrected the coding style nits. Chnages in V8: - Corrected the coding style nits pointed by Minkyu Kang. Changes in V9: - None Changes in V10: - None Changes in V11: - None Changes in V12: - None arch/arm/cpu/armv7/exynos/pinmux.c | 260 +++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/gpio.h | 143 ++++++++++++++-- arch/arm/include/asm/arch-exynos/periph.h | 3 + 3 files changed, 390 insertions(+), 16 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 74cc700..904177a 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -46,6 +46,42 @@ static void exynos5_uart_config(int peripheral) } } +static void exynos5420_uart_config(int peripheral) +{ + struct exynos5420_gpio_part1 *gpio1 = + (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); + struct s5p_gpio_bank *bank; + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + bank = &gpio1->a0; + start = 0; + count = 4; + break; + case PERIPH_ID_UART1: + bank = &gpio1->a0; + start = 4; + count = 4; + break; + case PERIPH_ID_UART2: + bank = &gpio1->a1; + start = 0; + count = 4; + break; + case PERIPH_ID_UART3: + bank = &gpio1->a1; + start = 4; + count = 2; + break; + } + + for (i = start; i < start + count; i++) { + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + } +} + static int exynos5_mmc_config(int peripheral, int flags) { struct exynos5_gpio_part1 *gpio1 = @@ -101,6 +137,75 @@ static int exynos5_mmc_config(int peripheral, int flags) return 0; } +static int exynos5420_mmc_config(int peripheral, int flags) +{ + struct exynos5420_gpio_part3 *gpio3 = + (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3(); + struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL; + int i, start; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + bank = &gpio3->c0; + bank_ext = &gpio3->c3; + start = 0; + break; + case PERIPH_ID_SDMMC1: + bank = &gpio3->c1; + bank_ext = &gpio3->d1; + start = 4; + break; + case PERIPH_ID_SDMMC2: + bank = &gpio3->c2; + bank_ext = NULL; + start = 0; + break; + default: + start = 0; + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + debug("SDMMC device %d does not support 8bit mode", + peripheral); + return -1; + } + + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = start; i <= (start + 3); i++) { + s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + } + } + + for (i = 0; i < 3; i++) { + /* + * MMC0 is intended to be used for eMMC. The + * card detect pin is used as a VDDEN signal to + * power on the eMMC. The 5420 iROM makes + * this same assumption. + */ + if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) { + s5p_gpio_set_value(bank, i, 1); + s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT); + } else { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + } + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + + for (i = 3; i <= 6; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + + return 0; +} + static void exynos5_sromc_config(int flags) { struct exynos5_gpio_part1 *gpio1 = @@ -216,6 +321,59 @@ static void exynos5_i2c_config(int peripheral, int flags) } } +static void exynos5420_i2c_config(int peripheral) +{ + struct exynos5420_gpio_part1 *gpio1 = + (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); + + switch (peripheral) { + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C8: + s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C9: + s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C10: + s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2)); + break; + } +} + static void exynos5_i2s_config(int peripheral) { int i; @@ -279,6 +437,58 @@ void exynos5_spi_config(int peripheral) } } +void exynos5420_spi_config(int peripheral) +{ + int cfg, pin, i; + struct s5p_gpio_bank *bank = NULL; + struct exynos5420_gpio_part1 *gpio1 = + (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); + struct exynos5420_gpio_part4 *gpio4 = + (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4(); + + switch (peripheral) { + case PERIPH_ID_SPI0: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI1: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 4; + break; + case PERIPH_ID_SPI2: + bank = &gpio1->b1; + cfg = GPIO_FUNC(0x5); + pin = 1; + break; + case PERIPH_ID_SPI3: + bank = &gpio4->f1; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI4: + cfg = 0; + pin = 0; + break; + default: + cfg = 0; + pin = 0; + debug("%s: invalid peripheral %d", __func__, peripheral); + return; + } + + if (peripheral != PERIPH_ID_SPI4) { + for (i = pin; i < pin + 4; i++) + s5p_gpio_cfg_pin(bank, i, cfg); + } else { + for (i = 0; i < 2; i++) { + s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4)); + } + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -325,6 +535,48 @@ static int exynos5_pinmux_config(int peripheral, int flags) return 0; } +static int exynos5420_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos5420_uart_config(peripheral); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + return exynos5420_mmc_config(peripheral, flags); + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + exynos5420_spi_config(peripheral); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + case PERIPH_ID_I2C8: + case PERIPH_ID_I2C9: + case PERIPH_ID_I2C10: + exynos5420_i2c_config(peripheral); + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + static void exynos4_i2c_config(int peripheral, int flags) { struct exynos4_gpio_part1 *gpio1 = @@ -475,13 +727,17 @@ static int exynos4_pinmux_config(int peripheral, int flags) int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) { - return exynos5_pinmux_config(peripheral, flags); + if (proid_is_exynos5420()) + return exynos5420_pinmux_config(peripheral, flags); + else if (proid_is_exynos5250()) + return exynos5_pinmux_config(peripheral, flags); } else if (cpu_is_exynos4()) { return exynos4_pinmux_config(peripheral, flags); } else { debug("pinmux functionality not supported\n"); - return -1; } + + return -1; } #ifdef CONFIG_OF_CONTROL diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index a1a7439..2a19852 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -127,6 +127,58 @@ struct exynos4x12_gpio_part4 { struct s5p_gpio_bank v4; }; +struct exynos5420_gpio_part1 { + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank a2; + struct s5p_gpio_bank b0; + struct s5p_gpio_bank b1; + struct s5p_gpio_bank b2; + struct s5p_gpio_bank b3; + struct s5p_gpio_bank b4; + struct s5p_gpio_bank h0; +}; + +struct exynos5420_gpio_part2 { + struct s5p_gpio_bank y7; /* 0x1340_0000 */ + struct s5p_gpio_bank res[0x5f]; /* */ + struct s5p_gpio_bank x0; /* 0x1340_0C00 */ + struct s5p_gpio_bank x1; /* 0x1340_0C20 */ + struct s5p_gpio_bank x2; /* 0x1340_0C40 */ + struct s5p_gpio_bank x3; /* 0x1340_0C60 */ +}; + +struct exynos5420_gpio_part3 { + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank c2; + struct s5p_gpio_bank c3; + struct s5p_gpio_bank c4; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank y0; + struct s5p_gpio_bank y1; + struct s5p_gpio_bank y2; + struct s5p_gpio_bank y3; + struct s5p_gpio_bank y4; + struct s5p_gpio_bank y5; + struct s5p_gpio_bank y6; +}; + +struct exynos5420_gpio_part4 { + struct s5p_gpio_bank e0; /* 0x1400_0000 */ + struct s5p_gpio_bank e1; /* 0x1400_0020 */ + struct s5p_gpio_bank f0; /* 0x1400_0040 */ + struct s5p_gpio_bank f1; /* 0x1400_0060 */ + struct s5p_gpio_bank g0; /* 0x1400_0080 */ + struct s5p_gpio_bank g1; /* 0x1400_00A0 */ + struct s5p_gpio_bank g2; /* 0x1400_00C0 */ + struct s5p_gpio_bank j4; /* 0x1400_00E0 */ +}; + +struct exynos5420_gpio_part5 { + struct s5p_gpio_bank z0; /* 0x0386_0000 */ +}; + struct exynos5_gpio_part1 { struct s5p_gpio_bank a0; struct s5p_gpio_bank a1; @@ -259,16 +311,67 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) + +/* EXYNOS5420 */ +#define exynos5420_gpio_part1_get_nr(bank, pin) \ + ((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\ + EXYNOS5420_GPIO_PART1_BASE)->bank)) \ + - EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + +#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos5420_gpio_part2_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\ + EXYNOS5420_GPIO_PART2_BASE)->bank)) \ + - EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX) + +#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos5420_gpio_part3_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\ + EXYNOS5420_GPIO_PART3_BASE)->bank)) \ + - EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX) + +#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos5420_gpio_part4_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\ + EXYNOS5420_GPIO_PART4_BASE)->bank)) \ + - EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX) + +#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + static inline unsigned int s5p_gpio_base(int nr) { if (cpu_is_exynos5()) { - if (nr < EXYNOS5_GPIO_PART1_MAX) - return EXYNOS5_GPIO_PART1_BASE; - else if (nr < EXYNOS5_GPIO_PART2_MAX) - return EXYNOS5_GPIO_PART2_BASE; - else - return EXYNOS5_GPIO_PART3_BASE; - + if (proid_is_exynos5420()) { + if (nr < EXYNOS5420_GPIO_PART1_MAX) + return EXYNOS5420_GPIO_PART1_BASE; + else if (nr < EXYNOS5420_GPIO_PART2_MAX) + return EXYNOS5420_GPIO_PART2_BASE; + else if (nr < EXYNOS5420_GPIO_PART3_MAX) + return EXYNOS5420_GPIO_PART3_BASE; + else + return EXYNOS5420_GPIO_PART4_BASE; + } else { + if (nr < EXYNOS5_GPIO_PART1_MAX) + return EXYNOS5_GPIO_PART1_BASE; + else if (nr < EXYNOS5_GPIO_PART2_MAX) + return EXYNOS5_GPIO_PART2_BASE; + else + return EXYNOS5_GPIO_PART3_BASE; + } } else if (cpu_is_exynos4()) { if (nr < EXYNOS4_GPIO_PART1_MAX) return EXYNOS4_GPIO_PART1_BASE; @@ -282,13 +385,25 @@ static inline unsigned int s5p_gpio_base(int nr) static inline unsigned int s5p_gpio_part_max(int nr) { if (cpu_is_exynos5()) { - if (nr < EXYNOS5_GPIO_PART1_MAX) - return 0; - else if (nr < EXYNOS5_GPIO_PART2_MAX) - return EXYNOS5_GPIO_PART1_MAX; - else - return EXYNOS5_GPIO_PART2_MAX; - + if (proid_is_exynos5420()) { + if (nr < EXYNOS5420_GPIO_PART1_MAX) + return 0; + else if (nr < EXYNOS5420_GPIO_PART2_MAX) + return EXYNOS5420_GPIO_PART1_MAX; + else if (nr < EXYNOS5420_GPIO_PART3_MAX) + return EXYNOS5420_GPIO_PART2_MAX; + else if (nr < EXYNOS5420_GPIO_PART4_MAX) + return EXYNOS5420_GPIO_PART3_MAX; + else + return EXYNOS5420_GPIO_PART4_MAX; + } else { + if (nr < EXYNOS5_GPIO_PART1_MAX) + return 0; + else if (nr < EXYNOS5_GPIO_PART2_MAX) + return EXYNOS5_GPIO_PART1_MAX; + else + return EXYNOS5_GPIO_PART2_MAX; + } } else if (cpu_is_exynos4()) { if (proid_is_exynos4412()) { if (nr < EXYNOS4X12_GPIO_PART1_MAX) diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 64bd8b7..30c7f18 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -34,6 +34,9 @@ enum periph_id { PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2, PERIPH_ID_SDMMC3, + PERIPH_ID_I2C8 = 87, + PERIPH_ID_I2C9, + PERIPH_ID_I2C10 = 203, PERIPH_ID_I2S0 = 98, PERIPH_ID_I2S1 = 99,