@@ -154,6 +154,8 @@ static void gic_set_irq(void *opaque, int irq, int level)
target = cm;
}
+ assert(irq >= GIC_NR_SGIS);
+
if (level == GIC_TEST_LEVEL(irq, cm)) {
return;
}
@@ -180,35 +182,50 @@ static void gic_set_running_irq(GICState *s, int cpu, int irq)
uint32_t gic_acknowledge_irq(GICState *s, int cpu)
{
- int new_irq;
+ int ret, irq, src;
int cm = 1 << cpu;
- new_irq = s->current_pending[cpu];
- if (new_irq == 1023
- || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) {
+ irq = s->current_pending[cpu];
+ if (irq == 1023
+ || GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) {
DPRINTF("ACK no pending IRQ\n");
return 1023;
}
- s->last_active[new_irq][cpu] = s->running_irq[cpu];
+ s->last_active[irq][cpu] = s->running_irq[cpu];
- cm = GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm;
- GIC_CLEAR_SW_PENDING(new_irq, cm);
+ cm = GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm;
+ GIC_CLEAR_SW_PENDING(irq, cm);
if (s->revision == REV_11MPCORE) {
/* Clear pending flags for both level and edge triggered interrupts.
* Level triggered IRQs will be reasserted once they become inactive.
*/
- GIC_CLEAR_PENDING(new_irq, cm);
+ GIC_CLEAR_PENDING(irq, cm);
+ ret = irq;
} else {
- /* Clear pending flags for edge-triggered and non-asserted
- * level-triggered interrupts
- */
- if (GIC_TEST_EDGE_TRIGGER(new_irq) || !GIC_TEST_LEVEL(new_irq, cpu)) {
- GIC_CLEAR_PENDING(new_irq, cm);
+ if (irq < GIC_NR_SGIS) {
+ /* Lookup the source CPU for the SGI and clear this in the
+ * sgi_pending map. Return the src and clear the overall pending
+ * state on this CPU if the SGI is not pending from any CPUs.
+ */
+ assert(s->sgi_pending[irq][cpu] != 0);
+ src = ctz32(s->sgi_pending[irq][cpu]);
+ s->sgi_pending[irq][cpu] &= ~(1 << src);
+ if (s->sgi_pending[irq][cpu] == 0)
+ GIC_CLEAR_PENDING(irq, cm);
+ ret = irq | ((src & 0x7) << 10);
+ } else {
+ /* Clear pending flags for edge-triggered and non-asserted
+ * level-triggered interrupts
+ */
+ if (GIC_TEST_EDGE_TRIGGER(irq) || !GIC_TEST_LEVEL(irq, cpu)) {
+ GIC_CLEAR_PENDING(irq, cm);
+ }
+ ret = irq;
}
}
- gic_set_running_irq(s, cpu, new_irq);
- DPRINTF("ACK %d\n", new_irq);
- return new_irq;
+ gic_set_running_irq(s, cpu, irq);
+ DPRINTF("ACK %d\n", irq);
+ return ret;
}
void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val)
@@ -574,6 +591,7 @@ static void gic_dist_writel(void *opaque, hwaddr offset,
int cpu;
int irq;
int mask;
+ int target_cpu;
cpu = gic_get_current_cpu(s);
irq = value & 0x3ff;
@@ -593,6 +611,12 @@ static void gic_dist_writel(void *opaque, hwaddr offset,
break;
}
GIC_SET_PENDING(irq, mask);
+ target_cpu = ctz32(mask);
+ while (target_cpu < GIC_NCPU) {
+ s->sgi_pending[irq][target_cpu] |= (1 << cpu);
+ mask &= ~(1 << target_cpu);
+ target_cpu = ctz32(mask);
+ }
gic_update(s);
return;
}
@@ -59,8 +59,8 @@ static const VMStateDescription vmstate_gic_irq_state = {
static const VMStateDescription vmstate_gic = {
.name = "arm_gic",
- .version_id = 4,
- .minimum_version_id = 4,
+ .version_id = 5,
+ .minimum_version_id = 5,
.pre_save = gic_pre_save,
.post_load = gic_post_load,
.fields = (VMStateField[]) {
@@ -72,6 +72,7 @@ static const VMStateDescription vmstate_gic = {
VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
VMSTATE_UINT16_2DARRAY(last_active, GICState, GIC_MAXIRQ, GIC_NCPU),
+ VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU),
VMSTATE_UINT16_ARRAY(running_irq, GICState, GIC_NCPU),
VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU),
@@ -56,6 +56,13 @@ typedef struct GICState {
uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
uint16_t last_active[GIC_MAXIRQ][GIC_NCPU];
+ /* For each SGI on the target CPU, we store 8 bits
+ * indicating which source CPUs have made this SGI
+ * pending on the target CPU. These correspond to
+ * the bytes in the GIC_SPENDSGIR* registers as
+ * read by the target CPU.
+ */
+ uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
uint16_t priority_mask[GIC_NCPU];
uint16_t running_irq[GIC_NCPU];
Right now the arm gic emulation doesn't keep track of the source of an SGI (which apparently Linux guests don't use, or they're fine with assuming CPU 0 always). Add the necessary matrix on the GICState structure and maintain the data when setting and clearing the pending state of an IRQ. Note that we always choose to present the source as the lowest-numbered CPU in case multiple cores have signalled the same SGI number to a core on the system. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> --- Changes [v3 -> v4]: - Assert that we are not messing with SGI state in gic_set_irq - Move bugfix of GICD_SPENDR to pending fixes patch - Get rid of the idea of git_clear_pending and handle clearing of source bits directly in gic_acknowledge_irq - Don't loop through CPUs to clear SGI sources - Return source CPU directly from gic_acknowledge_irq - Rename sgi_source to sgi_pending - Add comment (courtesey of Peter) to sgi_pending struct member. Changes [v2 -> v3]: - Changed ffs(x) - 1 to ctz32 - Changed cpu type to int in gic_clear_pending to avoid cast - Really try to fix the endless loop bug - Change gic_clear_pending to only clear the pending bit of SGIs if all CPUs do not have that IRQ pending from any CPUs. - Wrap long line in gic_internal.h - Fix bug allowing setting SGIs through the GICD_SPENDR Changes [v1 -> v2]: - Fixed endless loop bug - Bump version_id and minimum_version_id on vmstate struct hw/intc/arm_gic.c | 56 ++++++++++++++++++++++++++++------------ hw/intc/arm_gic_common.c | 5 ++-- include/hw/intc/arm_gic_common.h | 7 +++++ 3 files changed, 50 insertions(+), 18 deletions(-)