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[01/10] target-arm: A64: Add support for dumping AArch64 VFP register state

Message ID 1388267351-31818-2-git-send-email-peter.maydell@linaro.org
State Superseded
Headers show

Commit Message

Peter Maydell Dec. 28, 2013, 9:49 p.m. UTC 
From: Alexander Graf <agraf@suse.de>

When dumping the current CPU state, we can also get a request
to dump the FPU state along with the CPU's integer state.

Add support to dump the VFP state when that flag is set, so that
we can properly debug code that modifies floating point registers.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, rebased. Output all registers, two per-line.]
Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate-a64.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

Peter Maydell Dec. 30, 2013, 3:21 p.m. UTC | #1 
On 30 December 2013 14:58, Richard Henderson <rth@twiddle.net> wrote:
> On 12/28/2013 01:49 PM, Peter Maydell wrote:
>> +            uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
>> +            uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);
>> +            cpu_fprintf(f, "q%02d.0=%016" PRIx64 ":%016" PRIx64 " ",
>> +                        i, vlo, vhi);
>
> Why print them lo:hi instead of, what would seem to me, the more natural hi:lo.

Whoops, didn't read this patch quite closely enough :-)

> And what's that .0 qualifier doing on the end of an integer print field?

May be poorly edited remnant from a previous labelling of the two
halves as x.0 and x.1. Will remove.

thanks
-- PMM
diff mbox

Patch

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 40c6fc4..6f2b26e 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -119,6 +119,22 @@  void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
                 psr & PSTATE_C ? 'C' : '-',
                 psr & PSTATE_V ? 'V' : '-');
     cpu_fprintf(f, "\n");
+
+    if (flags & CPU_DUMP_FPU) {
+        int numvfpregs = 32;
+        for (i = 0; i < numvfpregs; i += 2) {
+            uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
+            uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);
+            cpu_fprintf(f, "q%02d.0=%016" PRIx64 ":%016" PRIx64 " ",
+                        i, vlo, vhi);
+            vlo = float64_val(env->vfp.regs[(i + 1) * 2]);
+            vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]);
+            cpu_fprintf(f, "q%02d.0=%016" PRIx64 ":%016" PRIx64 "\n",
+                        i + 1, vlo, vhi);
+        }
+        cpu_fprintf(f, "FPCR: %08x  FPSR: %08x\n",
+                    vfp_get_fpcr(env), vfp_get_fpsr(env));
+    }
 }
 
 static int get_mem_index(DisasContext *s)