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[v2,resend,1/5] ARM: add support for AT_HWCAP2 ELF auxv entry

Message ID 1389950591-4212-2-git-send-email-ard.biesheuvel@linaro.org
State Accepted
Commit b342ea4e4ff970518264c81eefd05f637e3f193a
Headers show

Commit Message

Ard Biesheuvel Jan. 17, 2014, 9:23 a.m. UTC
This enables AT_HWCAP2 for ARM. The generic support for this
new ELF auxv entry was added in commit 2171364d1a9 (powerpc:
Add HWCAP2 aux entry)

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/include/asm/hwcap.h      |  3 ++-
 arch/arm/include/uapi/asm/hwcap.h |  4 ++++
 arch/arm/kernel/setup.c           | 11 +++++++++++
 3 files changed, 17 insertions(+), 1 deletion(-)

Comments

Ard Biesheuvel Jan. 17, 2014, 3:26 p.m. UTC | #1
On 17 January 2014 16:07, Will Deacon <will.deacon@arm.com> wrote:
> Hi Ard,
>
> On Fri, Jan 17, 2014 at 09:23:07AM +0000, Ard Biesheuvel wrote:
>> This enables AT_HWCAP2 for ARM. The generic support for this
>> new ELF auxv entry was added in commit 2171364d1a9 (powerpc:
>> Add HWCAP2 aux entry)
>
> Does this require a corresponding change in libc so that the entry is
> actually used by the dynamic linker?
>

The auxv entry itself is already wired up [this includes getauxval()]

https://sourceware.org/git/?p=glibc.git;a=commit;h=1ae8bfe07c1a

The only thing that is lacking is a way to hook up ifunc relocation,
as the current prototype passes a single 32-bit quantity.
So either we change the prototype to (hwcap, hwcap2) or we need to
rely on getauxval() in ifunc selectors if they need to inspect hwcap2
diff mbox

Patch

diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index 6ff56eca3f1f..6e183fd269fb 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -9,6 +9,7 @@ 
  * instruction set this cpu supports.
  */
 #define ELF_HWCAP	(elf_hwcap)
-extern unsigned int elf_hwcap;
+#define ELF_HWCAP2	(elf_hwcap2)
+extern unsigned int elf_hwcap, elf_hwcap2;
 #endif
 #endif
diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 7dcc10d67253..87768b5cffd1 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -28,4 +28,8 @@ 
 #define HWCAP_LPAE	(1 << 20)
 #define HWCAP_EVTSTRM	(1 << 21)
 
+/*
+ * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2
+ */
+
 #endif /* _UAPI__ASMARM_HWCAP_H */
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 987a7f5bce5f..ce3049c89c18 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -100,6 +100,9 @@  EXPORT_SYMBOL(system_serial_high);
 unsigned int elf_hwcap __read_mostly;
 EXPORT_SYMBOL(elf_hwcap);
 
+unsigned int elf_hwcap2 __read_mostly;
+EXPORT_SYMBOL(elf_hwcap2);
+
 
 #ifdef MULTI_CPU
 struct processor processor __read_mostly;
@@ -992,6 +995,10 @@  static const char *hwcap_str[] = {
 	NULL
 };
 
+static const char *hwcap2_str[] = {
+	NULL
+};
+
 static int c_show(struct seq_file *m, void *v)
 {
 	int i, j;
@@ -1015,6 +1022,10 @@  static int c_show(struct seq_file *m, void *v)
 			if (elf_hwcap & (1 << j))
 				seq_printf(m, "%s ", hwcap_str[j]);
 
+		for (j = 0; hwcap2_str[j]; j++)
+			if (elf_hwcap2 & (1 << j))
+				seq_printf(m, "%s ", hwcap2_str[j]);
+
 		seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
 		seq_printf(m, "CPU architecture: %s\n",
 			   proc_arch[cpu_architecture()]);