| Message ID | 20200214115442.7166-2-yamada.masahiro@socionext.com |
|---|---|
| State | Accepted |
| Commit | 1320fa2e55d2180573fd48c71f097e1ec7dc4833 |
| Headers | show |
| Series | [1/3] ARM: uniphier: move NAND reset assertion to U-Boot proper from SPL | expand |
On Fri, Feb 14, 2020 at 8:55 PM Masahiro Yamada <yamada.masahiro at socionext.com> wrote: > > This workaround was previously needed for LD4, Pro4, sLD8, Pro5 > SoCs. The boot ROM does not touch this register for PXs2/LD6b or > later. > > Now that the reset signal of the Denali NAND controller is always > asserted in board_init() then deasserted in the driver, the > WRITE_PROTECT register gets back to the default value, which means > the write protect is deasserted. > > This workaround can go away entirely. > > Signed-off-by: Masahiro Yamada <yamada.masahiro at socionext.com> > --- Applied to u-boot-uniphier. > arch/arm/mach-uniphier/board_late_init.c | 17 ----------------- > 1 file changed, 17 deletions(-) > > diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c > index 793283058c35..378aad0c9c45 100644 > --- a/arch/arm/mach-uniphier/board_late_init.c > +++ b/arch/arm/mach-uniphier/board_late_init.c > @@ -14,25 +14,9 @@ > #include <stdio.h> > #include <linux/io.h> > #include <linux/printk.h> > -#include <../drivers/mtd/nand/raw/denali.h> > > #include "init.h" > > -static void nand_denali_wp_disable(void) > -{ > -#ifdef CONFIG_NAND_DENALI > - /* > - * Since the boot rom enables the write protection for NAND boot mode, > - * it must be disabled somewhere for "nand write", "nand erase", etc. > - * The workaround is here to not disturb the Denali NAND controller > - * driver just for a really SoC-specific thing. > - */ > - void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; > - > - writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT); > -#endif > -} > - > static void uniphier_set_env_fdt_file(void) > { > DECLARE_GLOBAL_DATA_PTR; > @@ -114,7 +98,6 @@ int board_late_init(void) > case BOOT_DEVICE_NAND: > printf("NAND Boot"); > env_set("bootdev", "nand"); > - nand_denali_wp_disable(); > break; > case BOOT_DEVICE_NOR: > printf("NOR Boot"); > -- > 2.17.1 >
diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 793283058c35..378aad0c9c45 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -14,25 +14,9 @@ #include <stdio.h> #include <linux/io.h> #include <linux/printk.h> -#include <../drivers/mtd/nand/raw/denali.h> #include "init.h" -static void nand_denali_wp_disable(void) -{ -#ifdef CONFIG_NAND_DENALI - /* - * Since the boot rom enables the write protection for NAND boot mode, - * it must be disabled somewhere for "nand write", "nand erase", etc. - * The workaround is here to not disturb the Denali NAND controller - * driver just for a really SoC-specific thing. - */ - void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; - - writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT); -#endif -} - static void uniphier_set_env_fdt_file(void) { DECLARE_GLOBAL_DATA_PTR; @@ -114,7 +98,6 @@ int board_late_init(void) case BOOT_DEVICE_NAND: printf("NAND Boot"); env_set("bootdev", "nand"); - nand_denali_wp_disable(); break; case BOOT_DEVICE_NOR: printf("NOR Boot");
This workaround was previously needed for LD4, Pro4, sLD8, Pro5 SoCs. The boot ROM does not touch this register for PXs2/LD6b or later. Now that the reset signal of the Denali NAND controller is always asserted in board_init() then deasserted in the driver, the WRITE_PROTECT register gets back to the default value, which means the write protect is deasserted. This workaround can go away entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro at socionext.com> --- arch/arm/mach-uniphier/board_late_init.c | 17 ----------------- 1 file changed, 17 deletions(-)