@@ -375,6 +375,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2088a-rdb-qspi.dtb \
fsl-ls1088a-rdb.dtb \
fsl-ls1088a-qds.dtb \
+ fsl-ls1088a-qds-21-x.dtb \
+ fsl-ls1088a-qds-29-x.dtb \
fsl-ls1028a-rdb.dtb \
fsl-ls1028a-qds.dtb \
fsl-lx2160a-rdb.dtb \
new file mode 100644
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1088AQDS device tree source for SERDES protocol 21.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1088a-qds-sd1-21.dtsi"
+
+/ {
+ model = "NXP Layerscape 1088a QDS Board (DTS 21-x)";
+ compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
+};
new file mode 100644
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1088AQDS device tree source for SERDES protocol 29.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1088a-qds-sd1-29.dtsi"
+
+/ {
+ model = "NXP Layerscape 1088a QDS Board (DTS 29-x)";
+ compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
+};
new file mode 100644
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1088AQDS device tree source for SERDES block #1 - protocol 21 (0x15)
+ *
+ * Copyright 2020 NXP
+ */
+
+#include "fsl-ls1088a-qds.dtsi"
+
+&dpmac1 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
+&dpmac2 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
+&dpmac4 {
+ status = "okay";
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+};
+
+&dpmac5 {
+ status = "okay";
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii-id";
+};
new file mode 100644
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1088AQDS device tree source for SERDES block #1 - protocol 29 (0x1d)
+ *
+ * Copyright 2020 NXP
+ */
+
+#include "fsl-ls1088a-qds.dtsi"
+
+&dpmac1 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
+&dpmac2 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
@@ -1,133 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * NXP ls1088a QDS board device tree source
+ * NXP ls1088a QDS default board device tree source
*
- * Copyright 2017 NXP
+ * Copyright 2020 NXP
*/
/dts-v1/;
-#include "fsl-ls1088a.dtsi"
-
/ {
model = "NXP Layerscape 1088a QDS Board";
compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
- aliases {
- spi0 = &qspi;
- spi1 = &dspi;
- };
-};
-
-&i2c0 {
- status = "okay";
- u-boot,dm-pre-reloc;
-
- i2c-mux at 77 {
- compatible = "nxp,pca9547";
- reg = <0x77>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c at 3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x3>;
-
- rtc at 51 {
- compatible = "pcf2127-rtc";
- reg = <0x51>;
- };
- };
- };
-};
-
-&ifc {
- #address-cells = <2>;
- #size-cells = <1>;
- /* NOR, NAND Flashes and FPGA on board */
- ranges = <0 0 0x5 0x80000000 0x08000000
- 2 0 0x5 0x30000000 0x00010000
- 3 0 0x5 0x20000000 0x00010000>;
- status = "okay";
-
- nor at 0,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "cfi-flash";
- reg = <0x0 0x0 0x8000000>;
- bank-width = <2>;
- device-width = <1>;
- };
-
- nand at 2,0 {
- compatible = "fsl,ifc-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x1 0x0 0x10000>;
- };
-
- fpga: board-control at 3,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus", "fsl,ls1088aqds-fpga",
- "fsl,fpga-qixis";
- reg = <0x2 0x0 0x0000100>;
- bank-width = <1>;
- device-width = <1>;
- ranges = <0 2 0 0x100>;
- };
-};
-
-&dspi {
- bus-num = <0>;
- status = "okay";
-
- dflash0: n25q128a {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <1000000>; /* input clock */
- };
-
- dflash1: sst25wf040b {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <3500000>;
- reg = <1>;
- };
-
- dflash2: en25s64 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <3500000>;
- reg = <2>;
- };
-};
-
-&qspi {
- bus-num = <0>;
- status = "okay";
-
- qflash0: s25fs512s at 0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
- };
-
- qflash1: s25fs512s at 1 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <1>;
- };
-};
-
-&sata {
- status = "okay";
};
new file mode 100644
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1088a QDS common board device tree source
+ *
+ * Copyright 2017-2020 NXP
+ */
+
+#include "fsl-ls1088a.dtsi"
+
+/ {
+ aliases {
+ spi0 = &qspi;
+ spi1 = &dspi;
+ };
+};
+
+&emdio1 {
+ status = "okay";
+};
+
+&emdio2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ fpga at 66 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "simple-mfd";
+ reg = <0x66>;
+
+ mux-mdio at 54 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mdio-mux-i2creg";
+ reg = <0x54>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5
+ mdio-parent-bus = <&emdio1>;
+
+ mdio at 00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x00>;
+
+ rgmii_phy1: ethernet-phy at 1 {
+ reg = <0x1>;
+ };
+ };
+ mdio at 20 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x20>;
+
+ rgmii_phy2: ethernet-phy at 2 {
+ reg = <0x2>;
+ };
+ };
+
+ emdio1_slot1: mdio at 40 { /* I/O Slot #1 */
+ reg = <0x40>;
+ device-name = "emdio1_slot1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emdio1_slot3: mdio at 60 { /* I/O Slot #3 */
+ reg = <0x60>;
+ device-name = "emdio1_slot3";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
+ i2c-mux at 77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ rtc at 51 {
+ compatible = "pcf2127-rtc";
+ reg = <0x51>;
+ };
+ };
+ };
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0 0 0x5 0x80000000 0x08000000
+ 2 0 0x5 0x30000000 0x00010000
+ 3 0 0x5 0x20000000 0x00010000>;
+ status = "okay";
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand at 2,0 {
+ compatible = "fsl,ifc-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1 0x0 0x10000>;
+ };
+
+ fpga: board-control at 3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus", "fsl,ls1088aqds-fpga",
+ "fsl,fpga-qixis";
+ reg = <0x2 0x0 0x0000100>;
+ bank-width = <1>;
+ device-width = <1>;
+ ranges = <0 2 0 0x100>;
+ };
+};
+
+&dspi {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <1000000>; /* input clock */
+ };
+
+ dflash1: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <3500000>;
+ reg = <1>;
+ };
+
+ dflash2: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <3500000>;
+ reg = <2>;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fs512s at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+
+ qflash1: s25fs512s at 1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <1>;
+ };
+};
+
+&sata {
+ status = "okay";
+};
@@ -742,3 +742,90 @@ void reset_phy(void)
mc_env_boot();
}
#endif /* CONFIG_RESET_PHY_R */
+
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+
+/* Structure to hold SERDES protocols supported in case of
+ * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+ *
+ * @serdes_block: the index of the SERDES block
+ * @serdes_protocol: the decimal value of the protocol supported
+ * @dts_needed: DTS notes describing the current configuration are needed
+ *
+ * When dts_needed is true, the board_fit_config_name_match() function
+ * will try to exactly match the current configuration of the block with a DTS
+ * name provided.
+ */
+static struct serdes_configuration {
+ u8 serdes_block;
+ u32 serdes_protocol;
+ bool dts_needed;
+} supported_protocols[] = {
+ /* Serdes block #1 */
+ {1, 21, true},
+ {1, 29, true},
+};
+
+#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
+
+static bool protocol_supported(u8 serdes_block, u32 protocol)
+{
+ struct serdes_configuration serdes_conf;
+ int i;
+
+ for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+ serdes_conf = supported_protocols[i];
+ if (serdes_conf.serdes_block == serdes_block &&
+ serdes_conf.serdes_protocol == protocol)
+ return true;
+ }
+
+ return false;
+}
+
+static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
+{
+ struct serdes_configuration serdes_conf;
+ int i;
+
+ for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+ serdes_conf = supported_protocols[i];
+ if (serdes_conf.serdes_block == serdes_block &&
+ serdes_conf.serdes_protocol == protocol) {
+ if (serdes_conf.dts_needed == true)
+ sprintf(str, "%u", protocol);
+ else
+ sprintf(str, "x");
+ return;
+ }
+ }
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ char expected_dts[100];
+ char srds_s1_str[2];
+ u32 srds_s1, cfg;
+
+ cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+ FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+ srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
+
+ /* Check for supported protocols. The default DTS will be used
+ * in this case
+ */
+ if (!protocol_supported(1, srds_s1))
+ return -1;
+
+ get_str_protocol(1, srds_s1, srds_s1_str);
+
+ sprintf(expected_dts, "fsl-ls1088a-qds-%s-x", srds_s1_str);
+
+ if (!strcmp(name, expected_dts))
+ return 0;
+
+ return -1;
+}
+#endif
Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2088a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds support for the on-board ports (DPMAC 1,2 and 4,5) found on the SERDES protocols 21(0x15) and 29(0x1d) for SD#1. On the LS1088AQDS board EMDIO1 is used with two onboard RGMII PHYs (Realtek RTL8211FD-CG), as well as 2 input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs. Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one of the 2 IO slots. As a consequence, a new node is added to describe register 0x54 as a MDIO mux controlled with child nodes describing all the IO slots as MDIO buses. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei <ioana.ciornei at nxp.com> --- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-ls1088a-qds-21-x.dts | 16 ++ arch/arm/dts/fsl-ls1088a-qds-29-x.dts | 16 ++ arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi | 30 ++++ arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi | 19 +++ arch/arm/dts/fsl-ls1088a-qds.dts | 124 +-------------- arch/arm/dts/fsl-ls1088a-qds.dtsi | 187 +++++++++++++++++++++++ board/freescale/ls1088a/eth_ls1088aqds.c | 87 +++++++++++ 8 files changed, 359 insertions(+), 122 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1088a-qds-21-x.dts create mode 100644 arch/arm/dts/fsl-ls1088a-qds-29-x.dts create mode 100644 arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-qds.dtsi