diff mbox series

[v2,8/9] riscv: sifive: fu540: add SPL configuration

Message ID 20200117124616.24695-9-pragnesh.patel@sifive.com
State New
Headers show
Series RISC-V SiFive FU540 support SPL | expand

Commit Message

Pragnesh Patel Jan. 17, 2020, 12:46 p.m. UTC 
This patch provides sifive_fu540_spl_defconfig which can support
U-boot SPL to boot from L2 LIM (0x0800_0000) and then boot U-boot
FIT image including OpenSBI FW_DYNAMIC firmware and U-Boot proper
images from MMC boot devices.

With sifive_fu540_spl_defconfig:

U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
image u-boot.itb from SD card (replace fw_payload.bin with u-boot.itb)
into RAM.

SPL related code is leverage from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)

Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
---
 arch/riscv/include/asm/csr.h       |   2 +
 board/sifive/fu540/Kconfig         |   8 +
 board/sifive/fu540/MAINTAINERS     |   1 +
 board/sifive/fu540/Makefile        |   5 +
 board/sifive/fu540/ddrregs.c       | 625 +++++++++++++++++++++++++++++
 board/sifive/fu540/fu540.c         |  27 +-
 board/sifive/fu540/spl.c           | 307 ++++++++++++++
 configs/sifive_fu540_spl_defconfig |  26 ++
 include/configs/sifive-fu540.h     |  18 +
 9 files changed, 1018 insertions(+), 1 deletion(-)
 create mode 100644 board/sifive/fu540/ddrregs.c
 create mode 100644 board/sifive/fu540/spl.c
 create mode 100644 configs/sifive_fu540_spl_defconfig

Comments

Anup Patel Jan. 20, 2020, 6:05 a.m. UTC | #1 
On Fri, Jan 17, 2020 at 6:18 PM Pragnesh Patel
<pragnesh.patel at sifive.com> wrote:
>
> This patch provides sifive_fu540_spl_defconfig which can support
> U-boot SPL to boot from L2 LIM (0x0800_0000) and then boot U-boot
> FIT image including OpenSBI FW_DYNAMIC firmware and U-Boot proper
> images from MMC boot devices.
>
> With sifive_fu540_spl_defconfig:
>
> U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
> u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
> image u-boot.itb from SD card (replace fw_payload.bin with u-boot.itb)
> into RAM.
>
> SPL related code is leverage from FSBL
> (https://github.com/sifive/freedom-u540-c000-bootloader.git)

Please look at my comments in PATCH7 regarding patch break-up.

>
> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
> ---
>  arch/riscv/include/asm/csr.h       |   2 +
>  board/sifive/fu540/Kconfig         |   8 +
>  board/sifive/fu540/MAINTAINERS     |   1 +
>  board/sifive/fu540/Makefile        |   5 +
>  board/sifive/fu540/ddrregs.c       | 625 +++++++++++++++++++++++++++++
>  board/sifive/fu540/fu540.c         |  27 +-
>  board/sifive/fu540/spl.c           | 307 ++++++++++++++
>  configs/sifive_fu540_spl_defconfig |  26 ++
>  include/configs/sifive-fu540.h     |  18 +
>  9 files changed, 1018 insertions(+), 1 deletion(-)
>  create mode 100644 board/sifive/fu540/ddrregs.c
>  create mode 100644 board/sifive/fu540/spl.c
>  create mode 100644 configs/sifive_fu540_spl_defconfig
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index d1520743a2..125c05dd8a 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -103,6 +103,8 @@
>  #define CSR_TIMEH              0xc81
>  #define CSR_INSTRETH           0xc82
>  #define CSR_MHARTID            0xf14
> +#define CSR_MCYCLE             0xb00
> +#define CSR_MCYCLEH            0xb80

This is a totally unrelated change. Please remove this change OR
send it as separate patch.

>
>  #ifndef __ASSEMBLY__
>
> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
> index 816a135b21..ac7c6bff37 100644
> --- a/board/sifive/fu540/Kconfig
> +++ b/board/sifive/fu540/Kconfig
> @@ -16,12 +16,20 @@ config SYS_SOC
>         default "fu540"
>
>  config SYS_TEXT_BASE
> +       default 0x80200000 if SPL
>         default 0x80000000 if !RISCV_SMODE
>         default 0x80200000 if RISCV_SMODE
>
> +config SPL_TEXT_BASE
> +       default 0x08000000
> +
> +config SPL_OPENSBI_LOAD_ADDR
> +       default 0x80000000
> +
>  config BOARD_SPECIFIC_OPTIONS # dummy
>         def_bool y
>         select GENERIC_RISCV
> +       select SUPPORT_SPL
>         imply CMD_DHCP
>         imply CMD_EXT2
>         imply CMD_EXT4
> diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS
> index 702d803ad8..42c3f3deb0 100644
> --- a/board/sifive/fu540/MAINTAINERS
> +++ b/board/sifive/fu540/MAINTAINERS
> @@ -7,3 +7,4 @@ S:      Maintained
>  F:     board/sifive/fu540/
>  F:     include/configs/sifive-fu540.h
>  F:     configs/sifive_fu540_defconfig
> +F:     configs/sifive_fu540_spl_defconfig

Palmer's email address is incorrect in this file.

I suggest to have separate patch for updating fu540/MAINTAINERS
file and not change fu540/MAINTAINERS here:
1. Add configs/sifive_fu540_spl_defconfig
2. Update Palmer's email address
3. Add yourself as first/primary maintainer for sifive/fu540 board support.
Other folks (including Me and Atish) are busy with other things so they
we are slow on U-Boot patch reviewes.

> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> index 6e1862c475..f01e731913 100644
> --- a/board/sifive/fu540/Makefile
> +++ b/board/sifive/fu540/Makefile
> @@ -3,3 +3,8 @@
>  # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>
>  obj-y  += fu540.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +obj-y += ddrregs.o
> +endif
> diff --git a/board/sifive/fu540/ddrregs.c b/board/sifive/fu540/ddrregs.c
> new file mode 100644
> index 0000000000..5c9c238aa1
> --- /dev/null
> +++ b/board/sifive/fu540/ddrregs.c
> @@ -0,0 +1,625 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + *
> + * Authors:
> + *   Pragnesh Patel <pragnesh.patel at sifive.com>
> + *   Troy Benjegerdes <troy.benjegerdes at sifive.com>
> + */
> +
> +#include <common.h>
> +
> +#include "regconfig-ctl.h"
> +#include "regconfig-phy.h"
> +
> +u32 ddr_phy_settings[1215] = {
> +       DENALI_PHY_00_DATA, DENALI_PHY_01_DATA, DENALI_PHY_02_DATA,
> +       DENALI_PHY_03_DATA, DENALI_PHY_04_DATA, DENALI_PHY_05_DATA,
> +       DENALI_PHY_06_DATA, DENALI_PHY_07_DATA, DENALI_PHY_08_DATA,
> +       DENALI_PHY_09_DATA,
> +       DENALI_PHY_10_DATA, DENALI_PHY_11_DATA, DENALI_PHY_12_DATA,
> +       DENALI_PHY_13_DATA, DENALI_PHY_14_DATA, DENALI_PHY_15_DATA,
> +       DENALI_PHY_16_DATA, DENALI_PHY_17_DATA, DENALI_PHY_18_DATA,
> +       DENALI_PHY_19_DATA,
> +       DENALI_PHY_20_DATA, DENALI_PHY_21_DATA, DENALI_PHY_22_DATA,
> +       DENALI_PHY_23_DATA, DENALI_PHY_24_DATA, DENALI_PHY_25_DATA,
> +       DENALI_PHY_26_DATA, DENALI_PHY_27_DATA, DENALI_PHY_28_DATA,
> +       DENALI_PHY_29_DATA,
> +       DENALI_PHY_30_DATA, DENALI_PHY_31_DATA, DENALI_PHY_32_DATA,
> +       DENALI_PHY_33_DATA, DENALI_PHY_34_DATA, DENALI_PHY_35_DATA,
> +       DENALI_PHY_36_DATA, DENALI_PHY_37_DATA, DENALI_PHY_38_DATA,
> +       DENALI_PHY_39_DATA,
> +       DENALI_PHY_40_DATA, DENALI_PHY_41_DATA, DENALI_PHY_42_DATA,
> +       DENALI_PHY_43_DATA, DENALI_PHY_44_DATA, DENALI_PHY_45_DATA,
> +       DENALI_PHY_46_DATA, DENALI_PHY_47_DATA, DENALI_PHY_48_DATA,
> +       DENALI_PHY_49_DATA,
> +       DENALI_PHY_50_DATA, DENALI_PHY_51_DATA, DENALI_PHY_52_DATA,
> +       DENALI_PHY_53_DATA, DENALI_PHY_54_DATA, DENALI_PHY_55_DATA,
> +       DENALI_PHY_56_DATA, DENALI_PHY_57_DATA, DENALI_PHY_58_DATA,
> +       DENALI_PHY_59_DATA,
> +       DENALI_PHY_60_DATA, DENALI_PHY_61_DATA, DENALI_PHY_62_DATA,
> +       DENALI_PHY_63_DATA, DENALI_PHY_64_DATA, DENALI_PHY_65_DATA,
> +       DENALI_PHY_66_DATA, DENALI_PHY_67_DATA, DENALI_PHY_68_DATA,
> +       DENALI_PHY_69_DATA,
> +       DENALI_PHY_70_DATA, DENALI_PHY_71_DATA, DENALI_PHY_72_DATA,
> +       DENALI_PHY_73_DATA, DENALI_PHY_74_DATA, DENALI_PHY_75_DATA,
> +       DENALI_PHY_76_DATA, DENALI_PHY_77_DATA, DENALI_PHY_78_DATA,
> +       DENALI_PHY_79_DATA,
> +       DENALI_PHY_80_DATA, DENALI_PHY_81_DATA, DENALI_PHY_82_DATA,
> +       DENALI_PHY_83_DATA, DENALI_PHY_84_DATA, DENALI_PHY_85_DATA,
> +       DENALI_PHY_86_DATA, DENALI_PHY_87_DATA, DENALI_PHY_88_DATA,
> +       DENALI_PHY_89_DATA,
> +       DENALI_PHY_90_DATA, DENALI_PHY_91_DATA, DENALI_PHY_92_DATA,
> +       DENALI_PHY_93_DATA, DENALI_PHY_94_DATA, DENALI_PHY_95_DATA,
> +       DENALI_PHY_96_DATA, DENALI_PHY_97_DATA, DENALI_PHY_98_DATA,
> +       DENALI_PHY_99_DATA,
> +
> +       DENALI_PHY_100_DATA, DENALI_PHY_101_DATA, DENALI_PHY_102_DATA,
> +       DENALI_PHY_103_DATA, DENALI_PHY_104_DATA, DENALI_PHY_105_DATA,
> +       DENALI_PHY_106_DATA, DENALI_PHY_107_DATA, DENALI_PHY_108_DATA,
> +       DENALI_PHY_109_DATA,
> +       DENALI_PHY_110_DATA, DENALI_PHY_111_DATA, DENALI_PHY_112_DATA,
> +       DENALI_PHY_113_DATA, DENALI_PHY_114_DATA, DENALI_PHY_115_DATA,
> +       DENALI_PHY_116_DATA, DENALI_PHY_117_DATA, DENALI_PHY_118_DATA,
> +       DENALI_PHY_119_DATA,
> +       DENALI_PHY_120_DATA, DENALI_PHY_121_DATA, DENALI_PHY_122_DATA,
> +       DENALI_PHY_123_DATA, DENALI_PHY_124_DATA, DENALI_PHY_125_DATA,
> +       DENALI_PHY_126_DATA, DENALI_PHY_127_DATA, DENALI_PHY_128_DATA,
> +       DENALI_PHY_129_DATA,
> +       DENALI_PHY_130_DATA, DENALI_PHY_131_DATA, DENALI_PHY_132_DATA,
> +       DENALI_PHY_133_DATA, DENALI_PHY_134_DATA, DENALI_PHY_135_DATA,
> +       DENALI_PHY_136_DATA, DENALI_PHY_137_DATA, DENALI_PHY_138_DATA,
> +       DENALI_PHY_139_DATA,
> +       DENALI_PHY_140_DATA, DENALI_PHY_141_DATA, DENALI_PHY_142_DATA,
> +       DENALI_PHY_143_DATA, DENALI_PHY_144_DATA, DENALI_PHY_145_DATA,
> +       DENALI_PHY_146_DATA, DENALI_PHY_147_DATA, DENALI_PHY_148_DATA,
> +       DENALI_PHY_149_DATA,
> +       DENALI_PHY_150_DATA, DENALI_PHY_151_DATA, DENALI_PHY_152_DATA,
> +       DENALI_PHY_153_DATA, DENALI_PHY_154_DATA, DENALI_PHY_155_DATA,
> +       DENALI_PHY_156_DATA, DENALI_PHY_157_DATA, DENALI_PHY_158_DATA,
> +       DENALI_PHY_159_DATA,
> +       DENALI_PHY_160_DATA, DENALI_PHY_161_DATA, DENALI_PHY_162_DATA,
> +       DENALI_PHY_163_DATA, DENALI_PHY_164_DATA, DENALI_PHY_165_DATA,
> +       DENALI_PHY_166_DATA, DENALI_PHY_167_DATA, DENALI_PHY_168_DATA,
> +       DENALI_PHY_169_DATA,
> +       DENALI_PHY_170_DATA, DENALI_PHY_171_DATA, DENALI_PHY_172_DATA,
> +       DENALI_PHY_173_DATA, DENALI_PHY_174_DATA, DENALI_PHY_175_DATA,
> +       DENALI_PHY_176_DATA, DENALI_PHY_177_DATA, DENALI_PHY_178_DATA,
> +       DENALI_PHY_179_DATA,
> +       DENALI_PHY_180_DATA, DENALI_PHY_181_DATA, DENALI_PHY_182_DATA,
> +       DENALI_PHY_183_DATA, DENALI_PHY_184_DATA, DENALI_PHY_185_DATA,
> +       DENALI_PHY_186_DATA, DENALI_PHY_187_DATA, DENALI_PHY_188_DATA,
> +       DENALI_PHY_189_DATA,
> +       DENALI_PHY_190_DATA, DENALI_PHY_191_DATA, DENALI_PHY_192_DATA,
> +       DENALI_PHY_193_DATA, DENALI_PHY_194_DATA, DENALI_PHY_195_DATA,
> +       DENALI_PHY_196_DATA, DENALI_PHY_197_DATA, DENALI_PHY_198_DATA,
> +       DENALI_PHY_199_DATA,
> +
> +       DENALI_PHY_200_DATA, DENALI_PHY_201_DATA, DENALI_PHY_202_DATA,
> +       DENALI_PHY_203_DATA, DENALI_PHY_204_DATA, DENALI_PHY_205_DATA,
> +       DENALI_PHY_206_DATA, DENALI_PHY_207_DATA, DENALI_PHY_208_DATA,
> +       DENALI_PHY_209_DATA,
> +       DENALI_PHY_210_DATA, DENALI_PHY_211_DATA, DENALI_PHY_212_DATA,
> +       DENALI_PHY_213_DATA, DENALI_PHY_214_DATA, DENALI_PHY_215_DATA,
> +       DENALI_PHY_216_DATA, DENALI_PHY_217_DATA, DENALI_PHY_218_DATA,
> +       DENALI_PHY_219_DATA,
> +       DENALI_PHY_220_DATA, DENALI_PHY_221_DATA, DENALI_PHY_222_DATA,
> +       DENALI_PHY_223_DATA, DENALI_PHY_224_DATA, DENALI_PHY_225_DATA,
> +       DENALI_PHY_226_DATA, DENALI_PHY_227_DATA, DENALI_PHY_228_DATA,
> +       DENALI_PHY_229_DATA,
> +       DENALI_PHY_230_DATA, DENALI_PHY_231_DATA, DENALI_PHY_232_DATA,
> +       DENALI_PHY_233_DATA, DENALI_PHY_234_DATA, DENALI_PHY_235_DATA,
> +       DENALI_PHY_236_DATA, DENALI_PHY_237_DATA, DENALI_PHY_238_DATA,
> +       DENALI_PHY_239_DATA,
> +       DENALI_PHY_240_DATA, DENALI_PHY_241_DATA, DENALI_PHY_242_DATA,
> +       DENALI_PHY_243_DATA, DENALI_PHY_244_DATA, DENALI_PHY_245_DATA,
> +       DENALI_PHY_246_DATA, DENALI_PHY_247_DATA, DENALI_PHY_248_DATA,
> +       DENALI_PHY_249_DATA,
> +       DENALI_PHY_250_DATA, DENALI_PHY_251_DATA, DENALI_PHY_252_DATA,
> +       DENALI_PHY_253_DATA, DENALI_PHY_254_DATA, DENALI_PHY_255_DATA,
> +       DENALI_PHY_256_DATA, DENALI_PHY_257_DATA, DENALI_PHY_258_DATA,
> +       DENALI_PHY_259_DATA,
> +       DENALI_PHY_260_DATA, DENALI_PHY_261_DATA, DENALI_PHY_262_DATA,
> +       DENALI_PHY_263_DATA, DENALI_PHY_264_DATA, DENALI_PHY_265_DATA,
> +       DENALI_PHY_266_DATA, DENALI_PHY_267_DATA, DENALI_PHY_268_DATA,
> +       DENALI_PHY_269_DATA,
> +       DENALI_PHY_270_DATA, DENALI_PHY_271_DATA, DENALI_PHY_272_DATA,
> +       DENALI_PHY_273_DATA, DENALI_PHY_274_DATA, DENALI_PHY_275_DATA,
> +       DENALI_PHY_276_DATA, DENALI_PHY_277_DATA, DENALI_PHY_278_DATA,
> +       DENALI_PHY_279_DATA,
> +       DENALI_PHY_280_DATA, DENALI_PHY_281_DATA, DENALI_PHY_282_DATA,
> +       DENALI_PHY_283_DATA, DENALI_PHY_284_DATA, DENALI_PHY_285_DATA,
> +       DENALI_PHY_286_DATA, DENALI_PHY_287_DATA, DENALI_PHY_288_DATA,
> +       DENALI_PHY_289_DATA,
> +       DENALI_PHY_290_DATA, DENALI_PHY_291_DATA, DENALI_PHY_292_DATA,
> +       DENALI_PHY_293_DATA, DENALI_PHY_294_DATA, DENALI_PHY_295_DATA,
> +       DENALI_PHY_296_DATA, DENALI_PHY_297_DATA, DENALI_PHY_298_DATA,
> +       DENALI_PHY_299_DATA,
> +
> +       DENALI_PHY_300_DATA, DENALI_PHY_301_DATA, DENALI_PHY_302_DATA,
> +       DENALI_PHY_303_DATA, DENALI_PHY_304_DATA, DENALI_PHY_305_DATA,
> +       DENALI_PHY_306_DATA, DENALI_PHY_307_DATA, DENALI_PHY_308_DATA,
> +       DENALI_PHY_309_DATA,
> +       DENALI_PHY_310_DATA, DENALI_PHY_311_DATA, DENALI_PHY_312_DATA,
> +       DENALI_PHY_313_DATA, DENALI_PHY_314_DATA, DENALI_PHY_315_DATA,
> +       DENALI_PHY_316_DATA, DENALI_PHY_317_DATA, DENALI_PHY_318_DATA,
> +       DENALI_PHY_319_DATA,
> +       DENALI_PHY_320_DATA, DENALI_PHY_321_DATA, DENALI_PHY_322_DATA,
> +       DENALI_PHY_323_DATA, DENALI_PHY_324_DATA, DENALI_PHY_325_DATA,
> +       DENALI_PHY_326_DATA, DENALI_PHY_327_DATA, DENALI_PHY_328_DATA,
> +       DENALI_PHY_329_DATA,
> +       DENALI_PHY_330_DATA, DENALI_PHY_331_DATA, DENALI_PHY_332_DATA,
> +       DENALI_PHY_333_DATA, DENALI_PHY_334_DATA, DENALI_PHY_335_DATA,
> +       DENALI_PHY_336_DATA, DENALI_PHY_337_DATA, DENALI_PHY_338_DATA,
> +       DENALI_PHY_339_DATA,
> +       DENALI_PHY_340_DATA, DENALI_PHY_341_DATA, DENALI_PHY_342_DATA,
> +       DENALI_PHY_343_DATA, DENALI_PHY_344_DATA, DENALI_PHY_345_DATA,
> +       DENALI_PHY_346_DATA, DENALI_PHY_347_DATA, DENALI_PHY_348_DATA,
> +       DENALI_PHY_349_DATA,
> +       DENALI_PHY_350_DATA, DENALI_PHY_351_DATA, DENALI_PHY_352_DATA,
> +       DENALI_PHY_353_DATA, DENALI_PHY_354_DATA, DENALI_PHY_355_DATA,
> +       DENALI_PHY_356_DATA, DENALI_PHY_357_DATA, DENALI_PHY_358_DATA,
> +       DENALI_PHY_359_DATA,
> +       DENALI_PHY_360_DATA, DENALI_PHY_361_DATA, DENALI_PHY_362_DATA,
> +       DENALI_PHY_363_DATA, DENALI_PHY_364_DATA, DENALI_PHY_365_DATA,
> +       DENALI_PHY_366_DATA, DENALI_PHY_367_DATA, DENALI_PHY_368_DATA,
> +       DENALI_PHY_369_DATA,
> +       DENALI_PHY_370_DATA, DENALI_PHY_371_DATA, DENALI_PHY_372_DATA,
> +       DENALI_PHY_373_DATA, DENALI_PHY_374_DATA, DENALI_PHY_375_DATA,
> +       DENALI_PHY_376_DATA, DENALI_PHY_377_DATA, DENALI_PHY_378_DATA,
> +       DENALI_PHY_379_DATA,
> +       DENALI_PHY_380_DATA, DENALI_PHY_381_DATA, DENALI_PHY_382_DATA,
> +       DENALI_PHY_383_DATA, DENALI_PHY_384_DATA, DENALI_PHY_385_DATA,
> +       DENALI_PHY_386_DATA, DENALI_PHY_387_DATA, DENALI_PHY_388_DATA,
> +       DENALI_PHY_389_DATA,
> +       DENALI_PHY_390_DATA, DENALI_PHY_391_DATA, DENALI_PHY_392_DATA,
> +       DENALI_PHY_393_DATA, DENALI_PHY_394_DATA, DENALI_PHY_395_DATA,
> +       DENALI_PHY_396_DATA, DENALI_PHY_397_DATA, DENALI_PHY_398_DATA,
> +       DENALI_PHY_399_DATA,
> +
> +       DENALI_PHY_400_DATA, DENALI_PHY_401_DATA, DENALI_PHY_402_DATA,
> +       DENALI_PHY_403_DATA, DENALI_PHY_404_DATA, DENALI_PHY_405_DATA,
> +       DENALI_PHY_406_DATA, DENALI_PHY_407_DATA, DENALI_PHY_408_DATA,
> +       DENALI_PHY_409_DATA,
> +       DENALI_PHY_410_DATA, DENALI_PHY_411_DATA, DENALI_PHY_412_DATA,
> +       DENALI_PHY_413_DATA, DENALI_PHY_414_DATA, DENALI_PHY_415_DATA,
> +       DENALI_PHY_416_DATA, DENALI_PHY_417_DATA, DENALI_PHY_418_DATA,
> +       DENALI_PHY_419_DATA,
> +       DENALI_PHY_420_DATA, DENALI_PHY_421_DATA, DENALI_PHY_422_DATA,
> +       DENALI_PHY_423_DATA, DENALI_PHY_424_DATA, DENALI_PHY_425_DATA,
> +       DENALI_PHY_426_DATA, DENALI_PHY_427_DATA, DENALI_PHY_428_DATA,
> +       DENALI_PHY_429_DATA,
> +       DENALI_PHY_430_DATA, DENALI_PHY_431_DATA, DENALI_PHY_432_DATA,
> +       DENALI_PHY_433_DATA, DENALI_PHY_434_DATA, DENALI_PHY_435_DATA,
> +       DENALI_PHY_436_DATA, DENALI_PHY_437_DATA, DENALI_PHY_438_DATA,
> +       DENALI_PHY_439_DATA,
> +       DENALI_PHY_440_DATA, DENALI_PHY_441_DATA, DENALI_PHY_442_DATA,
> +       DENALI_PHY_443_DATA, DENALI_PHY_444_DATA, DENALI_PHY_445_DATA,
> +       DENALI_PHY_446_DATA, DENALI_PHY_447_DATA, DENALI_PHY_448_DATA,
> +       DENALI_PHY_449_DATA,
> +       DENALI_PHY_450_DATA, DENALI_PHY_451_DATA, DENALI_PHY_452_DATA,
> +       DENALI_PHY_453_DATA, DENALI_PHY_454_DATA, DENALI_PHY_455_DATA,
> +       DENALI_PHY_456_DATA, DENALI_PHY_457_DATA, DENALI_PHY_458_DATA,
> +       DENALI_PHY_459_DATA,
> +       DENALI_PHY_460_DATA, DENALI_PHY_461_DATA, DENALI_PHY_462_DATA,
> +       DENALI_PHY_463_DATA, DENALI_PHY_464_DATA, DENALI_PHY_465_DATA,
> +       DENALI_PHY_466_DATA, DENALI_PHY_467_DATA, DENALI_PHY_468_DATA,
> +       DENALI_PHY_469_DATA,
> +       DENALI_PHY_470_DATA, DENALI_PHY_471_DATA, DENALI_PHY_472_DATA,
> +       DENALI_PHY_473_DATA, DENALI_PHY_474_DATA, DENALI_PHY_475_DATA,
> +       DENALI_PHY_476_DATA, DENALI_PHY_477_DATA, DENALI_PHY_478_DATA,
> +       DENALI_PHY_479_DATA,
> +       DENALI_PHY_480_DATA, DENALI_PHY_481_DATA, DENALI_PHY_482_DATA,
> +       DENALI_PHY_483_DATA, DENALI_PHY_484_DATA, DENALI_PHY_485_DATA,
> +       DENALI_PHY_486_DATA, DENALI_PHY_487_DATA, DENALI_PHY_488_DATA,
> +       DENALI_PHY_489_DATA,
> +       DENALI_PHY_490_DATA, DENALI_PHY_491_DATA, DENALI_PHY_492_DATA,
> +       DENALI_PHY_493_DATA, DENALI_PHY_494_DATA, DENALI_PHY_495_DATA,
> +       DENALI_PHY_496_DATA, DENALI_PHY_497_DATA, DENALI_PHY_498_DATA,
> +       DENALI_PHY_499_DATA,
> +
> +       DENALI_PHY_500_DATA, DENALI_PHY_501_DATA, DENALI_PHY_502_DATA,
> +       DENALI_PHY_503_DATA, DENALI_PHY_504_DATA, DENALI_PHY_505_DATA,
> +       DENALI_PHY_506_DATA, DENALI_PHY_507_DATA, DENALI_PHY_508_DATA,
> +       DENALI_PHY_509_DATA,
> +       DENALI_PHY_510_DATA, DENALI_PHY_511_DATA, DENALI_PHY_512_DATA,
> +       DENALI_PHY_513_DATA, DENALI_PHY_514_DATA, DENALI_PHY_515_DATA,
> +       DENALI_PHY_516_DATA, DENALI_PHY_517_DATA, DENALI_PHY_518_DATA,
> +       DENALI_PHY_519_DATA,
> +       DENALI_PHY_520_DATA, DENALI_PHY_521_DATA, DENALI_PHY_522_DATA,
> +       DENALI_PHY_523_DATA, DENALI_PHY_524_DATA, DENALI_PHY_525_DATA,
> +       DENALI_PHY_526_DATA, DENALI_PHY_527_DATA, DENALI_PHY_528_DATA,
> +       DENALI_PHY_529_DATA,
> +       DENALI_PHY_530_DATA, DENALI_PHY_531_DATA, DENALI_PHY_532_DATA,
> +       DENALI_PHY_533_DATA, DENALI_PHY_534_DATA, DENALI_PHY_535_DATA,
> +       DENALI_PHY_536_DATA, DENALI_PHY_537_DATA, DENALI_PHY_538_DATA,
> +       DENALI_PHY_539_DATA,
> +       DENALI_PHY_540_DATA, DENALI_PHY_541_DATA, DENALI_PHY_542_DATA,
> +       DENALI_PHY_543_DATA, DENALI_PHY_544_DATA, DENALI_PHY_545_DATA,
> +       DENALI_PHY_546_DATA, DENALI_PHY_547_DATA, DENALI_PHY_548_DATA,
> +       DENALI_PHY_549_DATA,
> +       DENALI_PHY_550_DATA, DENALI_PHY_551_DATA, DENALI_PHY_552_DATA,
> +       DENALI_PHY_553_DATA, DENALI_PHY_554_DATA, DENALI_PHY_555_DATA,
> +       DENALI_PHY_556_DATA, DENALI_PHY_557_DATA, DENALI_PHY_558_DATA,
> +       DENALI_PHY_559_DATA,
> +       DENALI_PHY_560_DATA, DENALI_PHY_561_DATA, DENALI_PHY_562_DATA,
> +       DENALI_PHY_563_DATA, DENALI_PHY_564_DATA, DENALI_PHY_565_DATA,
> +       DENALI_PHY_566_DATA, DENALI_PHY_567_DATA, DENALI_PHY_568_DATA,
> +       DENALI_PHY_569_DATA,
> +       DENALI_PHY_570_DATA, DENALI_PHY_571_DATA, DENALI_PHY_572_DATA,
> +       DENALI_PHY_573_DATA, DENALI_PHY_574_DATA, DENALI_PHY_575_DATA,
> +       DENALI_PHY_576_DATA, DENALI_PHY_577_DATA, DENALI_PHY_578_DATA,
> +       DENALI_PHY_579_DATA,
> +       DENALI_PHY_580_DATA, DENALI_PHY_581_DATA, DENALI_PHY_582_DATA,
> +       DENALI_PHY_583_DATA, DENALI_PHY_584_DATA, DENALI_PHY_585_DATA,
> +       DENALI_PHY_586_DATA, DENALI_PHY_587_DATA, DENALI_PHY_588_DATA,
> +       DENALI_PHY_589_DATA,
> +       DENALI_PHY_590_DATA, DENALI_PHY_591_DATA, DENALI_PHY_592_DATA,
> +       DENALI_PHY_593_DATA, DENALI_PHY_594_DATA, DENALI_PHY_595_DATA,
> +       DENALI_PHY_596_DATA, DENALI_PHY_597_DATA, DENALI_PHY_598_DATA,
> +       DENALI_PHY_599_DATA,
> +
> +       DENALI_PHY_600_DATA, DENALI_PHY_601_DATA, DENALI_PHY_602_DATA,
> +       DENALI_PHY_603_DATA, DENALI_PHY_604_DATA, DENALI_PHY_605_DATA,
> +       DENALI_PHY_606_DATA, DENALI_PHY_607_DATA, DENALI_PHY_608_DATA,
> +       DENALI_PHY_609_DATA,
> +       DENALI_PHY_610_DATA, DENALI_PHY_611_DATA, DENALI_PHY_612_DATA,
> +       DENALI_PHY_613_DATA, DENALI_PHY_614_DATA, DENALI_PHY_615_DATA,
> +       DENALI_PHY_616_DATA, DENALI_PHY_617_DATA, DENALI_PHY_618_DATA,
> +       DENALI_PHY_619_DATA,
> +       DENALI_PHY_620_DATA, DENALI_PHY_621_DATA, DENALI_PHY_622_DATA,
> +       DENALI_PHY_623_DATA, DENALI_PHY_624_DATA, DENALI_PHY_625_DATA,
> +       DENALI_PHY_626_DATA, DENALI_PHY_627_DATA, DENALI_PHY_628_DATA,
> +       DENALI_PHY_629_DATA,
> +       DENALI_PHY_630_DATA, DENALI_PHY_631_DATA, DENALI_PHY_632_DATA,
> +       DENALI_PHY_633_DATA, DENALI_PHY_634_DATA, DENALI_PHY_635_DATA,
> +       DENALI_PHY_636_DATA, DENALI_PHY_637_DATA, DENALI_PHY_638_DATA,
> +       DENALI_PHY_639_DATA,
> +       DENALI_PHY_640_DATA, DENALI_PHY_641_DATA, DENALI_PHY_642_DATA,
> +       DENALI_PHY_643_DATA, DENALI_PHY_644_DATA, DENALI_PHY_645_DATA,
> +       DENALI_PHY_646_DATA, DENALI_PHY_647_DATA, DENALI_PHY_648_DATA,
> +       DENALI_PHY_649_DATA,
> +       DENALI_PHY_650_DATA, DENALI_PHY_651_DATA, DENALI_PHY_652_DATA,
> +       DENALI_PHY_653_DATA, DENALI_PHY_654_DATA, DENALI_PHY_655_DATA,
> +       DENALI_PHY_656_DATA, DENALI_PHY_657_DATA, DENALI_PHY_658_DATA,
> +       DENALI_PHY_659_DATA,
> +       DENALI_PHY_660_DATA, DENALI_PHY_661_DATA, DENALI_PHY_662_DATA,
> +       DENALI_PHY_663_DATA, DENALI_PHY_664_DATA, DENALI_PHY_665_DATA,
> +       DENALI_PHY_666_DATA, DENALI_PHY_667_DATA, DENALI_PHY_668_DATA,
> +       DENALI_PHY_669_DATA,
> +       DENALI_PHY_670_DATA, DENALI_PHY_671_DATA, DENALI_PHY_672_DATA,
> +       DENALI_PHY_673_DATA, DENALI_PHY_674_DATA, DENALI_PHY_675_DATA,
> +       DENALI_PHY_676_DATA, DENALI_PHY_677_DATA, DENALI_PHY_678_DATA,
> +       DENALI_PHY_679_DATA,
> +       DENALI_PHY_680_DATA, DENALI_PHY_681_DATA, DENALI_PHY_682_DATA,
> +       DENALI_PHY_683_DATA, DENALI_PHY_684_DATA, DENALI_PHY_685_DATA,
> +       DENALI_PHY_686_DATA, DENALI_PHY_687_DATA, DENALI_PHY_688_DATA,
> +       DENALI_PHY_689_DATA,
> +       DENALI_PHY_690_DATA, DENALI_PHY_691_DATA, DENALI_PHY_692_DATA,
> +       DENALI_PHY_693_DATA, DENALI_PHY_694_DATA, DENALI_PHY_695_DATA,
> +       DENALI_PHY_696_DATA, DENALI_PHY_697_DATA, DENALI_PHY_698_DATA,
> +       DENALI_PHY_699_DATA,
> +
> +       DENALI_PHY_700_DATA, DENALI_PHY_701_DATA, DENALI_PHY_702_DATA,
> +       DENALI_PHY_703_DATA, DENALI_PHY_704_DATA, DENALI_PHY_705_DATA,
> +       DENALI_PHY_706_DATA, DENALI_PHY_707_DATA, DENALI_PHY_708_DATA,
> +       DENALI_PHY_709_DATA,
> +       DENALI_PHY_710_DATA, DENALI_PHY_711_DATA, DENALI_PHY_712_DATA,
> +       DENALI_PHY_713_DATA, DENALI_PHY_714_DATA, DENALI_PHY_715_DATA,
> +       DENALI_PHY_716_DATA, DENALI_PHY_717_DATA, DENALI_PHY_718_DATA,
> +       DENALI_PHY_719_DATA,
> +       DENALI_PHY_720_DATA, DENALI_PHY_721_DATA, DENALI_PHY_722_DATA,
> +       DENALI_PHY_723_DATA, DENALI_PHY_724_DATA, DENALI_PHY_725_DATA,
> +       DENALI_PHY_726_DATA, DENALI_PHY_727_DATA, DENALI_PHY_728_DATA,
> +       DENALI_PHY_729_DATA,
> +       DENALI_PHY_730_DATA, DENALI_PHY_731_DATA, DENALI_PHY_732_DATA,
> +       DENALI_PHY_733_DATA, DENALI_PHY_734_DATA, DENALI_PHY_735_DATA,
> +       DENALI_PHY_736_DATA, DENALI_PHY_737_DATA, DENALI_PHY_738_DATA,
> +       DENALI_PHY_739_DATA,
> +       DENALI_PHY_740_DATA, DENALI_PHY_741_DATA, DENALI_PHY_742_DATA,
> +       DENALI_PHY_743_DATA, DENALI_PHY_744_DATA, DENALI_PHY_745_DATA,
> +       DENALI_PHY_746_DATA, DENALI_PHY_747_DATA, DENALI_PHY_748_DATA,
> +       DENALI_PHY_749_DATA,
> +       DENALI_PHY_750_DATA, DENALI_PHY_751_DATA, DENALI_PHY_752_DATA,
> +       DENALI_PHY_753_DATA, DENALI_PHY_754_DATA, DENALI_PHY_755_DATA,
> +       DENALI_PHY_756_DATA, DENALI_PHY_757_DATA, DENALI_PHY_758_DATA,
> +       DENALI_PHY_759_DATA,
> +       DENALI_PHY_760_DATA, DENALI_PHY_761_DATA, DENALI_PHY_762_DATA,
> +       DENALI_PHY_763_DATA, DENALI_PHY_764_DATA, DENALI_PHY_765_DATA,
> +       DENALI_PHY_766_DATA, DENALI_PHY_767_DATA, DENALI_PHY_768_DATA,
> +       DENALI_PHY_769_DATA,
> +       DENALI_PHY_770_DATA, DENALI_PHY_771_DATA, DENALI_PHY_772_DATA,
> +       DENALI_PHY_773_DATA, DENALI_PHY_774_DATA, DENALI_PHY_775_DATA,
> +       DENALI_PHY_776_DATA, DENALI_PHY_777_DATA, DENALI_PHY_778_DATA,
> +       DENALI_PHY_779_DATA,
> +       DENALI_PHY_780_DATA, DENALI_PHY_781_DATA, DENALI_PHY_782_DATA,
> +       DENALI_PHY_783_DATA, DENALI_PHY_784_DATA, DENALI_PHY_785_DATA,
> +       DENALI_PHY_786_DATA, DENALI_PHY_787_DATA, DENALI_PHY_788_DATA,
> +       DENALI_PHY_789_DATA,
> +       DENALI_PHY_790_DATA, DENALI_PHY_791_DATA, DENALI_PHY_792_DATA,
> +       DENALI_PHY_793_DATA, DENALI_PHY_794_DATA, DENALI_PHY_795_DATA,
> +       DENALI_PHY_796_DATA, DENALI_PHY_797_DATA, DENALI_PHY_798_DATA,
> +       DENALI_PHY_799_DATA,
> +
> +       DENALI_PHY_800_DATA, DENALI_PHY_801_DATA, DENALI_PHY_802_DATA,
> +       DENALI_PHY_803_DATA, DENALI_PHY_804_DATA, DENALI_PHY_805_DATA,
> +       DENALI_PHY_806_DATA, DENALI_PHY_807_DATA, DENALI_PHY_808_DATA,
> +       DENALI_PHY_809_DATA,
> +       DENALI_PHY_810_DATA, DENALI_PHY_811_DATA, DENALI_PHY_812_DATA,
> +       DENALI_PHY_813_DATA, DENALI_PHY_814_DATA, DENALI_PHY_815_DATA,
> +       DENALI_PHY_816_DATA, DENALI_PHY_817_DATA, DENALI_PHY_818_DATA,
> +       DENALI_PHY_819_DATA,
> +       DENALI_PHY_820_DATA, DENALI_PHY_821_DATA, DENALI_PHY_822_DATA,
> +       DENALI_PHY_823_DATA, DENALI_PHY_824_DATA, DENALI_PHY_825_DATA,
> +       DENALI_PHY_826_DATA, DENALI_PHY_827_DATA, DENALI_PHY_828_DATA,
> +       DENALI_PHY_829_DATA,
> +       DENALI_PHY_830_DATA, DENALI_PHY_831_DATA, DENALI_PHY_832_DATA,
> +       DENALI_PHY_833_DATA, DENALI_PHY_834_DATA, DENALI_PHY_835_DATA,
> +       DENALI_PHY_836_DATA, DENALI_PHY_837_DATA, DENALI_PHY_838_DATA,
> +       DENALI_PHY_839_DATA,
> +       DENALI_PHY_840_DATA, DENALI_PHY_841_DATA, DENALI_PHY_842_DATA,
> +       DENALI_PHY_843_DATA, DENALI_PHY_844_DATA, DENALI_PHY_845_DATA,
> +       DENALI_PHY_846_DATA, DENALI_PHY_847_DATA, DENALI_PHY_848_DATA,
> +       DENALI_PHY_849_DATA,
> +       DENALI_PHY_850_DATA, DENALI_PHY_851_DATA, DENALI_PHY_852_DATA,
> +       DENALI_PHY_853_DATA, DENALI_PHY_854_DATA, DENALI_PHY_855_DATA,
> +       DENALI_PHY_856_DATA, DENALI_PHY_857_DATA, DENALI_PHY_858_DATA,
> +       DENALI_PHY_859_DATA,
> +       DENALI_PHY_860_DATA, DENALI_PHY_861_DATA, DENALI_PHY_862_DATA,
> +       DENALI_PHY_863_DATA, DENALI_PHY_864_DATA, DENALI_PHY_865_DATA,
> +       DENALI_PHY_866_DATA, DENALI_PHY_867_DATA, DENALI_PHY_868_DATA,
> +       DENALI_PHY_869_DATA,
> +       DENALI_PHY_870_DATA, DENALI_PHY_871_DATA, DENALI_PHY_872_DATA,
> +       DENALI_PHY_873_DATA, DENALI_PHY_874_DATA, DENALI_PHY_875_DATA,
> +       DENALI_PHY_876_DATA, DENALI_PHY_877_DATA, DENALI_PHY_878_DATA,
> +       DENALI_PHY_879_DATA,
> +       DENALI_PHY_880_DATA, DENALI_PHY_881_DATA, DENALI_PHY_882_DATA,
> +       DENALI_PHY_883_DATA, DENALI_PHY_884_DATA, DENALI_PHY_885_DATA,
> +       DENALI_PHY_886_DATA, DENALI_PHY_887_DATA, DENALI_PHY_888_DATA,
> +       DENALI_PHY_889_DATA,
> +       DENALI_PHY_890_DATA, DENALI_PHY_891_DATA, DENALI_PHY_892_DATA,
> +       DENALI_PHY_893_DATA, DENALI_PHY_894_DATA, DENALI_PHY_895_DATA,
> +       DENALI_PHY_896_DATA, DENALI_PHY_897_DATA, DENALI_PHY_898_DATA,
> +       DENALI_PHY_899_DATA,
> +
> +       DENALI_PHY_900_DATA, DENALI_PHY_901_DATA, DENALI_PHY_902_DATA,
> +       DENALI_PHY_903_DATA, DENALI_PHY_904_DATA, DENALI_PHY_905_DATA,
> +       DENALI_PHY_906_DATA, DENALI_PHY_907_DATA, DENALI_PHY_908_DATA,
> +       DENALI_PHY_909_DATA,
> +       DENALI_PHY_910_DATA, DENALI_PHY_911_DATA, DENALI_PHY_912_DATA,
> +       DENALI_PHY_913_DATA, DENALI_PHY_914_DATA, DENALI_PHY_915_DATA,
> +       DENALI_PHY_916_DATA, DENALI_PHY_917_DATA, DENALI_PHY_918_DATA,
> +       DENALI_PHY_919_DATA,
> +       DENALI_PHY_920_DATA, DENALI_PHY_921_DATA, DENALI_PHY_922_DATA,
> +       DENALI_PHY_923_DATA, DENALI_PHY_924_DATA, DENALI_PHY_925_DATA,
> +       DENALI_PHY_926_DATA, DENALI_PHY_927_DATA, DENALI_PHY_928_DATA,
> +       DENALI_PHY_929_DATA,
> +       DENALI_PHY_930_DATA, DENALI_PHY_931_DATA, DENALI_PHY_932_DATA,
> +       DENALI_PHY_933_DATA, DENALI_PHY_934_DATA, DENALI_PHY_935_DATA,
> +       DENALI_PHY_936_DATA, DENALI_PHY_937_DATA, DENALI_PHY_938_DATA,
> +       DENALI_PHY_939_DATA,
> +       DENALI_PHY_940_DATA, DENALI_PHY_941_DATA, DENALI_PHY_942_DATA,
> +       DENALI_PHY_943_DATA, DENALI_PHY_944_DATA, DENALI_PHY_945_DATA,
> +       DENALI_PHY_946_DATA, DENALI_PHY_947_DATA, DENALI_PHY_948_DATA,
> +       DENALI_PHY_949_DATA,
> +       DENALI_PHY_950_DATA, DENALI_PHY_951_DATA, DENALI_PHY_952_DATA,
> +       DENALI_PHY_953_DATA, DENALI_PHY_954_DATA, DENALI_PHY_955_DATA,
> +       DENALI_PHY_956_DATA, DENALI_PHY_957_DATA, DENALI_PHY_958_DATA,
> +       DENALI_PHY_959_DATA,
> +       DENALI_PHY_960_DATA, DENALI_PHY_961_DATA, DENALI_PHY_962_DATA,
> +       DENALI_PHY_963_DATA, DENALI_PHY_964_DATA, DENALI_PHY_965_DATA,
> +       DENALI_PHY_966_DATA, DENALI_PHY_967_DATA, DENALI_PHY_968_DATA,
> +       DENALI_PHY_969_DATA,
> +       DENALI_PHY_970_DATA, DENALI_PHY_971_DATA, DENALI_PHY_972_DATA,
> +       DENALI_PHY_973_DATA, DENALI_PHY_974_DATA, DENALI_PHY_975_DATA,
> +       DENALI_PHY_976_DATA, DENALI_PHY_977_DATA, DENALI_PHY_978_DATA,
> +       DENALI_PHY_979_DATA,
> +       DENALI_PHY_980_DATA, DENALI_PHY_981_DATA, DENALI_PHY_982_DATA,
> +       DENALI_PHY_983_DATA, DENALI_PHY_984_DATA, DENALI_PHY_985_DATA,
> +       DENALI_PHY_986_DATA, DENALI_PHY_987_DATA, DENALI_PHY_988_DATA,
> +       DENALI_PHY_989_DATA,
> +       DENALI_PHY_990_DATA, DENALI_PHY_991_DATA, DENALI_PHY_992_DATA,
> +       DENALI_PHY_993_DATA, DENALI_PHY_994_DATA, DENALI_PHY_995_DATA,
> +       DENALI_PHY_996_DATA, DENALI_PHY_997_DATA, DENALI_PHY_998_DATA,
> +       DENALI_PHY_999_DATA,
> +
> +       DENALI_PHY_1000_DATA, DENALI_PHY_1001_DATA, DENALI_PHY_1002_DATA,
> +       DENALI_PHY_1003_DATA, DENALI_PHY_1004_DATA, DENALI_PHY_1005_DATA,
> +       DENALI_PHY_1006_DATA, DENALI_PHY_1007_DATA, DENALI_PHY_1008_DATA,
> +       DENALI_PHY_1009_DATA,
> +       DENALI_PHY_1010_DATA, DENALI_PHY_1011_DATA, DENALI_PHY_1012_DATA,
> +       DENALI_PHY_1013_DATA, DENALI_PHY_1014_DATA, DENALI_PHY_1015_DATA,
> +       DENALI_PHY_1016_DATA, DENALI_PHY_1017_DATA, DENALI_PHY_1018_DATA,
> +       DENALI_PHY_1019_DATA,
> +       DENALI_PHY_1020_DATA, DENALI_PHY_1021_DATA, DENALI_PHY_1022_DATA,
> +       DENALI_PHY_1023_DATA, DENALI_PHY_1024_DATA, DENALI_PHY_1025_DATA,
> +       DENALI_PHY_1026_DATA, DENALI_PHY_1027_DATA, DENALI_PHY_1028_DATA,
> +       DENALI_PHY_1029_DATA,
> +       DENALI_PHY_1030_DATA, DENALI_PHY_1031_DATA, DENALI_PHY_1032_DATA,
> +       DENALI_PHY_1033_DATA, DENALI_PHY_1034_DATA, DENALI_PHY_1035_DATA,
> +       DENALI_PHY_1036_DATA, DENALI_PHY_1037_DATA, DENALI_PHY_1038_DATA,
> +       DENALI_PHY_1039_DATA,
> +       DENALI_PHY_1040_DATA, DENALI_PHY_1041_DATA, DENALI_PHY_1042_DATA,
> +       DENALI_PHY_1043_DATA, DENALI_PHY_1044_DATA, DENALI_PHY_1045_DATA,
> +       DENALI_PHY_1046_DATA, DENALI_PHY_1047_DATA, DENALI_PHY_1048_DATA,
> +       DENALI_PHY_1049_DATA,
> +       DENALI_PHY_1050_DATA, DENALI_PHY_1051_DATA, DENALI_PHY_1052_DATA,
> +       DENALI_PHY_1053_DATA, DENALI_PHY_1054_DATA, DENALI_PHY_1055_DATA,
> +       DENALI_PHY_1056_DATA, DENALI_PHY_1057_DATA, DENALI_PHY_1058_DATA,
> +       DENALI_PHY_1059_DATA,
> +       DENALI_PHY_1060_DATA, DENALI_PHY_1061_DATA, DENALI_PHY_1062_DATA,
> +       DENALI_PHY_1063_DATA, DENALI_PHY_1064_DATA, DENALI_PHY_1065_DATA,
> +       DENALI_PHY_1066_DATA, DENALI_PHY_1067_DATA, DENALI_PHY_1068_DATA,
> +       DENALI_PHY_1069_DATA,
> +       DENALI_PHY_1070_DATA, DENALI_PHY_1071_DATA, DENALI_PHY_1072_DATA,
> +       DENALI_PHY_1073_DATA, DENALI_PHY_1074_DATA, DENALI_PHY_1075_DATA,
> +       DENALI_PHY_1076_DATA, DENALI_PHY_1077_DATA, DENALI_PHY_1078_DATA,
> +       DENALI_PHY_1079_DATA,
> +       DENALI_PHY_1080_DATA, DENALI_PHY_1081_DATA, DENALI_PHY_1082_DATA,
> +       DENALI_PHY_1083_DATA, DENALI_PHY_1084_DATA, DENALI_PHY_1085_DATA,
> +       DENALI_PHY_1086_DATA, DENALI_PHY_1087_DATA, DENALI_PHY_1088_DATA,
> +       DENALI_PHY_1089_DATA,
> +       DENALI_PHY_1090_DATA, DENALI_PHY_1091_DATA, DENALI_PHY_1092_DATA,
> +       DENALI_PHY_1093_DATA, DENALI_PHY_1094_DATA, DENALI_PHY_1095_DATA,
> +       DENALI_PHY_1096_DATA, DENALI_PHY_1097_DATA, DENALI_PHY_1098_DATA,
> +       DENALI_PHY_1099_DATA,
> +
> +       DENALI_PHY_1100_DATA, DENALI_PHY_1101_DATA, DENALI_PHY_1102_DATA,
> +       DENALI_PHY_1103_DATA, DENALI_PHY_1104_DATA, DENALI_PHY_1105_DATA,
> +       DENALI_PHY_1106_DATA, DENALI_PHY_1107_DATA, DENALI_PHY_1108_DATA,
> +       DENALI_PHY_1109_DATA,
> +       DENALI_PHY_1110_DATA, DENALI_PHY_1111_DATA, DENALI_PHY_1112_DATA,
> +       DENALI_PHY_1113_DATA, DENALI_PHY_1114_DATA, DENALI_PHY_1115_DATA,
> +       DENALI_PHY_1116_DATA, DENALI_PHY_1117_DATA, DENALI_PHY_1118_DATA,
> +       DENALI_PHY_1119_DATA,
> +       DENALI_PHY_1120_DATA, DENALI_PHY_1121_DATA, DENALI_PHY_1122_DATA,
> +       DENALI_PHY_1123_DATA, DENALI_PHY_1124_DATA, DENALI_PHY_1125_DATA,
> +       DENALI_PHY_1126_DATA, DENALI_PHY_1127_DATA, DENALI_PHY_1128_DATA,
> +       DENALI_PHY_1129_DATA,
> +       DENALI_PHY_1130_DATA, DENALI_PHY_1131_DATA, DENALI_PHY_1132_DATA,
> +       DENALI_PHY_1133_DATA, DENALI_PHY_1134_DATA, DENALI_PHY_1135_DATA,
> +       DENALI_PHY_1136_DATA, DENALI_PHY_1137_DATA, DENALI_PHY_1138_DATA,
> +       DENALI_PHY_1139_DATA,
> +       DENALI_PHY_1140_DATA, DENALI_PHY_1141_DATA, DENALI_PHY_1142_DATA,
> +       DENALI_PHY_1143_DATA, DENALI_PHY_1144_DATA, DENALI_PHY_1145_DATA,
> +       DENALI_PHY_1146_DATA, DENALI_PHY_1147_DATA, DENALI_PHY_1148_DATA,
> +       DENALI_PHY_1149_DATA,
> +       DENALI_PHY_1150_DATA, DENALI_PHY_1151_DATA, DENALI_PHY_1152_DATA,
> +       DENALI_PHY_1153_DATA, DENALI_PHY_1154_DATA, DENALI_PHY_1155_DATA,
> +       DENALI_PHY_1156_DATA, DENALI_PHY_1157_DATA, DENALI_PHY_1158_DATA,
> +       DENALI_PHY_1159_DATA,
> +       DENALI_PHY_1160_DATA, DENALI_PHY_1161_DATA, DENALI_PHY_1162_DATA,
> +       DENALI_PHY_1163_DATA, DENALI_PHY_1164_DATA, DENALI_PHY_1165_DATA,
> +       DENALI_PHY_1166_DATA, DENALI_PHY_1167_DATA, DENALI_PHY_1168_DATA,
> +       DENALI_PHY_1169_DATA,
> +       DENALI_PHY_1170_DATA, DENALI_PHY_1171_DATA, DENALI_PHY_1172_DATA,
> +       DENALI_PHY_1173_DATA, DENALI_PHY_1174_DATA, DENALI_PHY_1175_DATA,
> +       DENALI_PHY_1176_DATA, DENALI_PHY_1177_DATA, DENALI_PHY_1178_DATA,
> +       DENALI_PHY_1179_DATA,
> +       DENALI_PHY_1180_DATA, DENALI_PHY_1181_DATA, DENALI_PHY_1182_DATA,
> +       DENALI_PHY_1183_DATA, DENALI_PHY_1184_DATA, DENALI_PHY_1185_DATA,
> +       DENALI_PHY_1186_DATA, DENALI_PHY_1187_DATA, DENALI_PHY_1188_DATA,
> +       DENALI_PHY_1189_DATA,
> +       DENALI_PHY_1190_DATA, DENALI_PHY_1191_DATA, DENALI_PHY_1192_DATA,
> +       DENALI_PHY_1193_DATA, DENALI_PHY_1194_DATA, DENALI_PHY_1195_DATA,
> +       DENALI_PHY_1196_DATA, DENALI_PHY_1197_DATA, DENALI_PHY_1198_DATA,
> +       DENALI_PHY_1199_DATA,
> +
> +       DENALI_PHY_1200_DATA, DENALI_PHY_1201_DATA, DENALI_PHY_1202_DATA,
> +       DENALI_PHY_1203_DATA, DENALI_PHY_1204_DATA, DENALI_PHY_1205_DATA,
> +       DENALI_PHY_1206_DATA, DENALI_PHY_1207_DATA, DENALI_PHY_1208_DATA,
> +       DENALI_PHY_1209_DATA,
> +       DENALI_PHY_1210_DATA, DENALI_PHY_1211_DATA, DENALI_PHY_1212_DATA,
> +       DENALI_PHY_1213_DATA, DENALI_PHY_1214_DATA
> +};
> +
> +u32 ddr_ctl_settings[265] = {
> +       DENALI_CTL_00_DATA, DENALI_CTL_01_DATA, DENALI_CTL_02_DATA,
> +       DENALI_CTL_03_DATA, DENALI_CTL_04_DATA, DENALI_CTL_05_DATA,
> +       DENALI_CTL_06_DATA, DENALI_CTL_07_DATA, DENALI_CTL_08_DATA,
> +       DENALI_CTL_09_DATA,
> +       DENALI_CTL_10_DATA, DENALI_CTL_11_DATA, DENALI_CTL_12_DATA,
> +       DENALI_CTL_13_DATA, DENALI_CTL_14_DATA, DENALI_CTL_15_DATA,
> +       DENALI_CTL_16_DATA, DENALI_CTL_17_DATA, DENALI_CTL_18_DATA,
> +       DENALI_CTL_19_DATA,
> +       DENALI_CTL_20_DATA, DENALI_CTL_21_DATA, DENALI_CTL_22_DATA,
> +       DENALI_CTL_23_DATA, DENALI_CTL_24_DATA, DENALI_CTL_25_DATA,
> +       DENALI_CTL_26_DATA, DENALI_CTL_27_DATA, DENALI_CTL_28_DATA,
> +       DENALI_CTL_29_DATA,
> +       DENALI_CTL_30_DATA, DENALI_CTL_31_DATA, DENALI_CTL_32_DATA,
> +       DENALI_CTL_33_DATA, DENALI_CTL_34_DATA, DENALI_CTL_35_DATA,
> +       DENALI_CTL_36_DATA, DENALI_CTL_37_DATA, DENALI_CTL_38_DATA,
> +       DENALI_CTL_39_DATA,
> +       DENALI_CTL_40_DATA, DENALI_CTL_41_DATA, DENALI_CTL_42_DATA,
> +       DENALI_CTL_43_DATA, DENALI_CTL_44_DATA, DENALI_CTL_45_DATA,
> +       DENALI_CTL_46_DATA, DENALI_CTL_47_DATA, DENALI_CTL_48_DATA,
> +       DENALI_CTL_49_DATA,
> +       DENALI_CTL_50_DATA, DENALI_CTL_51_DATA, DENALI_CTL_52_DATA,
> +       DENALI_CTL_53_DATA, DENALI_CTL_54_DATA, DENALI_CTL_55_DATA,
> +       DENALI_CTL_56_DATA, DENALI_CTL_57_DATA, DENALI_CTL_58_DATA,
> +       DENALI_CTL_59_DATA,
> +       DENALI_CTL_60_DATA, DENALI_CTL_61_DATA, DENALI_CTL_62_DATA,
> +       DENALI_CTL_63_DATA, DENALI_CTL_64_DATA, DENALI_CTL_65_DATA,
> +       DENALI_CTL_66_DATA, DENALI_CTL_67_DATA, DENALI_CTL_68_DATA,
> +       DENALI_CTL_69_DATA,
> +       DENALI_CTL_70_DATA, DENALI_CTL_71_DATA, DENALI_CTL_72_DATA,
> +       DENALI_CTL_73_DATA, DENALI_CTL_74_DATA, DENALI_CTL_75_DATA,
> +       DENALI_CTL_76_DATA, DENALI_CTL_77_DATA, DENALI_CTL_78_DATA,
> +       DENALI_CTL_79_DATA,
> +       DENALI_CTL_80_DATA, DENALI_CTL_81_DATA, DENALI_CTL_82_DATA,
> +       DENALI_CTL_83_DATA, DENALI_CTL_84_DATA, DENALI_CTL_85_DATA,
> +       DENALI_CTL_86_DATA, DENALI_CTL_87_DATA, DENALI_CTL_88_DATA,
> +       DENALI_CTL_89_DATA,
> +       DENALI_CTL_90_DATA, DENALI_CTL_91_DATA, DENALI_CTL_92_DATA,
> +       DENALI_CTL_93_DATA, DENALI_CTL_94_DATA, DENALI_CTL_95_DATA,
> +       DENALI_CTL_96_DATA, DENALI_CTL_97_DATA, DENALI_CTL_98_DATA,
> +       DENALI_CTL_99_DATA,
> +
> +       DENALI_CTL_100_DATA, DENALI_CTL_101_DATA, DENALI_CTL_102_DATA,
> +       DENALI_CTL_103_DATA, DENALI_CTL_104_DATA, DENALI_CTL_105_DATA,
> +       DENALI_CTL_106_DATA, DENALI_CTL_107_DATA, DENALI_CTL_108_DATA,
> +       DENALI_CTL_109_DATA,
> +       DENALI_CTL_110_DATA, DENALI_CTL_111_DATA, DENALI_CTL_112_DATA,
> +       DENALI_CTL_113_DATA, DENALI_CTL_114_DATA, DENALI_CTL_115_DATA,
> +       DENALI_CTL_116_DATA, DENALI_CTL_117_DATA, DENALI_CTL_118_DATA,
> +       DENALI_CTL_119_DATA,
> +       DENALI_CTL_120_DATA, DENALI_CTL_121_DATA, DENALI_CTL_122_DATA,
> +       DENALI_CTL_123_DATA, DENALI_CTL_124_DATA, DENALI_CTL_125_DATA,
> +       DENALI_CTL_126_DATA, DENALI_CTL_127_DATA, DENALI_CTL_128_DATA,
> +       DENALI_CTL_129_DATA,
> +       DENALI_CTL_130_DATA, DENALI_CTL_131_DATA, DENALI_CTL_132_DATA,
> +       DENALI_CTL_133_DATA, DENALI_CTL_134_DATA, DENALI_CTL_135_DATA,
> +       DENALI_CTL_136_DATA, DENALI_CTL_137_DATA, DENALI_CTL_138_DATA,
> +       DENALI_CTL_139_DATA,
> +       DENALI_CTL_140_DATA, DENALI_CTL_141_DATA, DENALI_CTL_142_DATA,
> +       DENALI_CTL_143_DATA, DENALI_CTL_144_DATA, DENALI_CTL_145_DATA,
> +       DENALI_CTL_146_DATA, DENALI_CTL_147_DATA, DENALI_CTL_148_DATA,
> +       DENALI_CTL_149_DATA,
> +       DENALI_CTL_150_DATA, DENALI_CTL_151_DATA, DENALI_CTL_152_DATA,
> +       DENALI_CTL_153_DATA, DENALI_CTL_154_DATA, DENALI_CTL_155_DATA,
> +       DENALI_CTL_156_DATA, DENALI_CTL_157_DATA, DENALI_CTL_158_DATA,
> +       DENALI_CTL_159_DATA,
> +       DENALI_CTL_160_DATA, DENALI_CTL_161_DATA, DENALI_CTL_162_DATA,
> +       DENALI_CTL_163_DATA, DENALI_CTL_164_DATA, DENALI_CTL_165_DATA,
> +       DENALI_CTL_166_DATA, DENALI_CTL_167_DATA, DENALI_CTL_168_DATA,
> +       DENALI_CTL_169_DATA,
> +       DENALI_CTL_170_DATA, DENALI_CTL_171_DATA, DENALI_CTL_172_DATA,
> +       DENALI_CTL_173_DATA, DENALI_CTL_174_DATA, DENALI_CTL_175_DATA,
> +       DENALI_CTL_176_DATA, DENALI_CTL_177_DATA, DENALI_CTL_178_DATA,
> +       DENALI_CTL_179_DATA,
> +       DENALI_CTL_180_DATA, DENALI_CTL_181_DATA, DENALI_CTL_182_DATA,
> +       DENALI_CTL_183_DATA, DENALI_CTL_184_DATA, DENALI_CTL_185_DATA,
> +       DENALI_CTL_186_DATA, DENALI_CTL_187_DATA, DENALI_CTL_188_DATA,
> +       DENALI_CTL_189_DATA,
> +       DENALI_CTL_190_DATA, DENALI_CTL_191_DATA, DENALI_CTL_192_DATA,
> +       DENALI_CTL_193_DATA, DENALI_CTL_194_DATA, DENALI_CTL_195_DATA,
> +       DENALI_CTL_196_DATA, DENALI_CTL_197_DATA, DENALI_CTL_198_DATA,
> +       DENALI_CTL_199_DATA,
> +
> +       DENALI_CTL_200_DATA, DENALI_CTL_201_DATA, DENALI_CTL_202_DATA,
> +       DENALI_CTL_203_DATA, DENALI_CTL_204_DATA, DENALI_CTL_205_DATA,
> +       DENALI_CTL_206_DATA, DENALI_CTL_207_DATA, DENALI_CTL_208_DATA,
> +       DENALI_CTL_209_DATA,
> +       DENALI_CTL_210_DATA, DENALI_CTL_211_DATA, DENALI_CTL_212_DATA,
> +       DENALI_CTL_213_DATA, DENALI_CTL_214_DATA, DENALI_CTL_215_DATA,
> +       DENALI_CTL_216_DATA, DENALI_CTL_217_DATA, DENALI_CTL_218_DATA,
> +       DENALI_CTL_219_DATA,
> +       DENALI_CTL_220_DATA, DENALI_CTL_221_DATA, DENALI_CTL_222_DATA,
> +       DENALI_CTL_223_DATA, DENALI_CTL_224_DATA, DENALI_CTL_225_DATA,
> +       DENALI_CTL_226_DATA, DENALI_CTL_227_DATA, DENALI_CTL_228_DATA,
> +       DENALI_CTL_229_DATA,
> +       DENALI_CTL_230_DATA, DENALI_CTL_231_DATA, DENALI_CTL_232_DATA,
> +       DENALI_CTL_233_DATA, DENALI_CTL_234_DATA, DENALI_CTL_235_DATA,
> +       DENALI_CTL_236_DATA, DENALI_CTL_237_DATA, DENALI_CTL_238_DATA,
> +       DENALI_CTL_239_DATA,
> +       DENALI_CTL_240_DATA, DENALI_CTL_241_DATA, DENALI_CTL_242_DATA,
> +       DENALI_CTL_243_DATA, DENALI_CTL_244_DATA, DENALI_CTL_245_DATA,
> +       DENALI_CTL_246_DATA, DENALI_CTL_247_DATA, DENALI_CTL_248_DATA,
> +       DENALI_CTL_249_DATA,
> +       DENALI_CTL_250_DATA, DENALI_CTL_251_DATA, DENALI_CTL_252_DATA,
> +       DENALI_CTL_253_DATA, DENALI_CTL_254_DATA, DENALI_CTL_255_DATA,
> +       DENALI_CTL_256_DATA, DENALI_CTL_257_DATA, DENALI_CTL_258_DATA,
> +       DENALI_CTL_259_DATA,
> +       DENALI_CTL_260_DATA, DENALI_CTL_261_DATA, DENALI_CTL_262_DATA,
> +       DENALI_CTL_263_DATA, DENALI_CTL_264_DATA
> +};
> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> index 3a5e74f1fb..7cd81e46cc 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -11,6 +11,8 @@
>  #include <linux/delay.h>
>  #include <linux/io.h>
>  #include <misc.h>
> +#include <spl.h>
> +#include "fu540-memory-map.h"
>
>  /*
>   * This define is a value used for error/unknown serial.
> @@ -110,7 +112,30 @@ int misc_init_r(void)
>
>  int board_init(void)
>  {
> -       /* For now nothing to do here. */
> +       /* enable all cache ways */
> +       ccache_enable_ways(CCACHE_CTRL_ADDR, 15);
> +       return 0;
> +}
> +
> +#ifdef CONFIG_SPL
> +void board_boot_order(u32 *spl_boot_list)
> +{
> +       u8 i;
> +       u32 boot_devices[] = {
> +#ifdef CONFIG_SPL_MMC_SUPPORT
> +               BOOT_DEVICE_MMC1,
> +#endif
> +       };
>
> +       for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
> +               spl_boot_list[i] = boot_devices[i];
> +}
> +#endif
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> +       /* boot using first FIT config */
>         return 0;
>  }
> +#endif
> diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c
> new file mode 100644
> index 0000000000..beeadcae82
> --- /dev/null
> +++ b/board/sifive/fu540/spl.c
> @@ -0,0 +1,307 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + *
> + * Authors:
> + *   Pragnesh Patel <pragnesh.patel at sifive.com>
> + *   Troy Benjegerdes <troy.benjegerdes at sifive.com>
> + */
> +
> +#include <common.h>
> +#include <spl.h>
> +#include <misc.h>
> +
> +#include "ux00ddr.h"
> +#include "fu540-memory-map.h"
> +
> +#define DDR_SIZE  (8UL * 1024UL * 1024UL * 1024UL)
> +#define DDRCTLPLL_F 55
> +#define DDRCTLPLL_Q 2
> +
> +#define PHY_NRESET 0x1000
> +#define FIRST_SLOT  0xfe
> +#define LAST_SLOT   0x80
> +
> +static const uintptr_t uart_devices[] = {
> +       UART0_CTRL_ADDR,
> +       UART1_CTRL_ADDR,
> +};
> +
> +unsigned int serial_to_burn = ~0;
> +
> +static inline int ux00prci_select_corepll(volatile u32 *coreclkselreg,
> +                                         volatile u32 *corepllcfg,
> +                                         volatile u32 *corepllout,
> +                                         u32 pllconfigval)
> +{
> +       (*corepllcfg) = pllconfigval;
> +
> +       // Wait for lock
> +       while (((*corepllcfg) & (PLL_LOCK(1))) == 0)
> +               ;
> +
> +       u32 core_out =
> +               (PLLOUT_DIV(PLLOUT_DIV_default)) |
> +               (PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
> +               (PLLOUT_CLK_EN(1));
> +       (*corepllout) = core_out;
> +
> +       // Set CORECLKSELREG to select COREPLL
> +       (*coreclkselreg) = PLL_CORECLKSEL_COREPLL;
> +
> +       return 0;
> +}
> +
> +static inline int ux00prci_select_corepll_500mhz(volatile u32 *coreclkselreg,
> +                                                volatile u32 *corepllcfg,
> +                                                volatile u32 *corepllout)
> +{
> +       /*
> +        * CORE pll init
> +        * Set corepll 33MHz -> 1GHz
> +        */
> +
> +       u32 core500mhz =
> +               (PLL_R(0)) |
> +               (PLL_F(59)) |            /*4000MHz VCO*/
> +               (PLL_Q(3)) |             /* /8 Output divider */
> +               (PLL_RANGE(0x4)) |
> +               (PLL_BYPASS(0)) |
> +               (PLL_FSE(1));
> +
> +       return ux00prci_select_corepll(coreclkselreg, corepllcfg, corepllout,
> +                       core500mhz);
> +}
> +
> +static inline int ux00prci_select_corepll_1ghz(volatile u32 *coreclkselreg,
> +                                              volatile u32 *corepllcfg,
> +                                              volatile u32 *corepllout)
> +{
> +       /*
> +        * CORE pll init
> +        * Set corepll 33MHz -> 1GHz
> +        */
> +
> +       u32 core1ghz =
> +               (PLL_R(0)) |
> +               (PLL_F(59)) |            /*4000MHz VCO*/
> +               (PLL_Q(2)) |             /* /4 Output divider */
> +               (PLL_RANGE(0x4)) |
> +               (PLL_BYPASS(0)) |
> +               (PLL_FSE(1));
> +
> +       return ux00prci_select_corepll(coreclkselreg, corepllcfg, corepllout,
> +                       core1ghz);
> +}
> +
> +/*
> + * Get smallest clock divisor that divides input_hz to a quotient less than or
> + * equal to max_target_hz;
> + */
> +static inline unsigned int uart_min_clk_divisor(u64 input_hz, u64 max_target_hz)
> +{
> +       u64 quotient = (input_hz + max_target_hz - 1) / (max_target_hz);
> +
> +       // Avoid underflow
> +       if (quotient == 0)
> +               return 0;
> +       else
> +               return quotient - 1;
> +}
> +
> +/**
> + * Scale uart clock dividers before changing core PLL.
> + */
> +void update_uart_clock_dividers(unsigned int peripheral_input_khz)
> +{
> +       unsigned int uart_target_hz = 115200ULL;
> +       unsigned int uart_div = uart_min_clk_divisor(peripheral_input_khz *
> +                       1000ULL, uart_target_hz);
> +
> +       for (size_t i = 0; i < ARRAY_SIZE(uart_devices); i++)
> +               _REG32(uart_devices[i], UART_REG_DIV) = uart_div;
> +}
> +
> +long nsec_per_cyc = 300; // 33.333MHz
> +void nsleep(long nsec)
> +{
> +       long step = nsec_per_cyc * 2; // 2 instructions per loop iteration
> +
> +       while (nsec > 0)
> +               nsec -= step;
> +}
> +
> +void init_clk_and_ddr(void)
> +{
> +       // PRCI init
> +
> +       unsigned long peripheral_input_khz;
> +
> +       // Check Reset Values (lock don't care)
> +       u32 pll_default =
> +               (PLL_R(PLL_R_default)) |
> +               (PLL_F(PLL_F_default)) |
> +               (PLL_Q(PLL_Q_default)) |
> +               (PLL_RANGE(PLL_RANGE_default)) |
> +               (PLL_BYPASS(PLL_BYPASS_default)) |
> +               (PLL_FSE(PLL_FSE_default));
> +       u32 lockmask = ~PLL_LOCK(1);
> +       u32 pllout_default =
> +               (PLLOUT_DIV(PLLOUT_DIV_default)) |
> +               (PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
> +               (PLLOUT_CLK_EN(PLLOUT_CLK_EN_default));
> +
> +       if ((UX00PRCI_REG(UX00PRCI_COREPLLCFG)     ^ pll_default) & lockmask)
> +               return;
> +       if ((UX00PRCI_REG(UX00PRCI_COREPLLOUT)     ^ pllout_default))
> +               return;
> +       if ((UX00PRCI_REG(UX00PRCI_DDRPLLCFG)      ^ pll_default) & lockmask)
> +               return;
> +       if ((UX00PRCI_REG(UX00PRCI_DDRPLLOUT)      ^ pllout_default))
> +               return;
> +       if (((UX00PRCI_REG(UX00PRCI_GEMGXLPLLCFG)) ^ pll_default) & lockmask)
> +               return;
> +       if (((UX00PRCI_REG(UX00PRCI_GEMGXLPLLOUT)) ^ pllout_default))
> +               return;
> +
> +       //CORE pll init
> +       // If tlclksel is set for 2:1 operation,
> +       // Set corepll 33Mhz -> 1GHz
> +       // Otherwise, set corepll 33MHz -> 500MHz.
> +
> +       if (UX00PRCI_REG(UX00PRCI_CLKMUXSTATUSREG) & CLKMUX_STATUS_TLCLKSEL) {
> +               nsec_per_cyc = 2;
> +               peripheral_input_khz = 500000; // peripheral_clk = tlclk
> +               update_uart_clock_dividers(peripheral_input_khz);
> +               ux00prci_select_corepll_500mhz
> +                       (&UX00PRCI_REG(UX00PRCI_CORECLKSELREG),
> +                        &UX00PRCI_REG(UX00PRCI_COREPLLCFG),
> +                        &UX00PRCI_REG(UX00PRCI_COREPLLOUT));
> +       } else {
> +               nsec_per_cyc = 1;
> +               peripheral_input_khz = (1000000 / 2); // peripheral_clk = tlclk
> +               update_uart_clock_dividers(peripheral_input_khz);
> +
> +               ux00prci_select_corepll_1ghz
> +                       (&UX00PRCI_REG(UX00PRCI_CORECLKSELREG),
> +                        &UX00PRCI_REG(UX00PRCI_COREPLLCFG),
> +                        &UX00PRCI_REG(UX00PRCI_COREPLLOUT));
> +       }
> +
> +       //
> +       //DDR init
> +       //
> +
> +       u32 ddrctlmhz =
> +               (PLL_R(0)) |
> +               (PLL_F(DDRCTLPLL_F)) |
> +               (PLL_Q(DDRCTLPLL_Q)) |
> +               (PLL_RANGE(0x4)) |
> +               (PLL_BYPASS(0)) |
> +               (PLL_FSE(1));
> +       UX00PRCI_REG(UX00PRCI_DDRPLLCFG) = ddrctlmhz;
> +
> +       // Wait for lock
> +       while ((UX00PRCI_REG(UX00PRCI_DDRPLLCFG) & PLL_LOCK(1)) == 0)
> +               ;
> +
> +       u32 ddrctl_out =
> +               (PLLOUT_DIV(PLLOUT_DIV_default)) |
> +               (PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
> +               (PLLOUT_CLK_EN(1));
> +       (UX00PRCI_REG(UX00PRCI_DDRPLLOUT)) = ddrctl_out;
> +
> +       //Release DDR reset.
> +       UX00PRCI_REG(UX00PRCI_DEVICESRESETREG) |=
> +               DEVICESRESET_DDR_CTRL_RST_N(1);
> +
> +       // HACK to get the '1 full controller clock cycle'.
> +       asm volatile ("fence");
> +       UX00PRCI_REG(UX00PRCI_DEVICESRESETREG) |= DEVICESRESET_DDR_AXI_RST_N(1)
> +               | DEVICESRESET_DDR_AHB_RST_N(1) | DEVICESRESET_DDR_PHY_RST_N(1);
> +       // HACK to get the '1 full controller clock cycle'.
> +       asm volatile ("fence");
> +       // These take like 16 cycles to actually propagate. We can't go sending
> +       // stuff before they come out of reset. So wait. (TODO: Add a register
> +       // to read the current reset states, or DDR Control device?)
> +       for (int i = 0; i < 256; i++)
> +               asm volatile ("nop");
> +
> +       ux00ddr_writeregmap(UX00DDR_CTRL_ADDR, ddr_ctl_settings,
> +                           ddr_phy_settings);
> +       ux00ddr_disableaxireadinterleave(UX00DDR_CTRL_ADDR);
> +
> +       ux00ddr_disableoptimalrmodw(UX00DDR_CTRL_ADDR);
> +
> +       ux00ddr_enablewriteleveling(UX00DDR_CTRL_ADDR);
> +       ux00ddr_enablereadleveling(UX00DDR_CTRL_ADDR);
> +       ux00ddr_enablereadlevelinggate(UX00DDR_CTRL_ADDR);
> +       if (ux00ddr_getdramclass(UX00DDR_CTRL_ADDR) == DRAM_CLASS_DDR4)
> +               ux00ddr_enablevreftraining(UX00DDR_CTRL_ADDR);
> +       //mask off interrupts for leveling completion
> +       ux00ddr_mask_leveling_completed_interrupt(UX00DDR_CTRL_ADDR);
> +
> +       ux00ddr_mask_mc_init_complete_interrupt(UX00DDR_CTRL_ADDR);
> +       ux00ddr_mask_outofrange_interrupts(UX00DDR_CTRL_ADDR);
> +       ux00ddr_setuprangeprotection(UX00DDR_CTRL_ADDR, DDR_SIZE);
> +       ux00ddr_mask_port_command_error_interrupt(UX00DDR_CTRL_ADDR);
> +
> +       const u64 ddr_size = DDR_SIZE;
> +       const u64 ddr_end = CONFIG_SYS_SDRAM_BASE + ddr_size;
> +
> +       ux00ddr_start(UX00DDR_CTRL_ADDR, PHYSICAL_FILTER_CTRL_ADDR, ddr_end);
> +       ux00ddr_phy_fixup(UX00DDR_CTRL_ADDR);
> +
> +       //
> +       //GEMGXL init
> +       //
> +       u32 gemgxl125mhz =
> +               (PLL_R(0)) |
> +               (PLL_F(59)) |  /*4000Mhz VCO*/
> +               (PLL_Q(5)) |   /* /32 */
> +               (PLL_RANGE(0x4)) |
> +               (PLL_BYPASS(0)) |
> +               (PLL_FSE(1));
> +       UX00PRCI_REG(UX00PRCI_GEMGXLPLLCFG) = gemgxl125mhz;
> +
> +       // Wait for lock
> +       while ((UX00PRCI_REG(UX00PRCI_GEMGXLPLLCFG) & PLL_LOCK(1)) == 0)
> +               ;
> +
> +       u32 gemgxlctl_out =
> +               (PLLOUT_DIV(PLLOUT_DIV_default)) |
> +               (PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
> +               (PLLOUT_CLK_EN(1));
> +       UX00PRCI_REG(UX00PRCI_GEMGXLPLLOUT) = gemgxlctl_out;
> +
> +       //Release GEMGXL reset (set bit DEVICESRESET_GEMGXL to 1)
> +       UX00PRCI_REG(UX00PRCI_DEVICESRESETREG) |= DEVICESRESET_GEMGXL_RST_N(1);
> +
> +       // VSC8541 PHY reset sequence; leave pull-down active for 2ms
> +       nsleep(2000000);
> +       // Set GPIO 12 (PHY NRESET) to OE=1 and OVAL=1
> +       GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET;
> +       GPIO_REG(GPIO_OUTPUT_EN) |= PHY_NRESET;
> +       nsleep(100);
> +
> +       // Procmon => core clock
> +       UX00PRCI_REG(UX00PRCI_PROCMONCFG) = 0x1 << 24;
> +
> +       // Post the serial number and build info
> +       UART0_REG(UART_REG_TXCTRL) = UART_TXEN;
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> +       int ret;
> +
> +       ret = spl_early_init();
> +       if (ret)
> +               panic("spl_early_init() failed: %d\n", ret);
> +
> +       arch_cpu_init_dm();
> +
> +       init_clk_and_ddr();
> +
> +       preloader_console_init();
> +}
> diff --git a/configs/sifive_fu540_spl_defconfig b/configs/sifive_fu540_spl_defconfig
> new file mode 100644
> index 0000000000..4053743f4c
> --- /dev/null
> +++ b/configs/sifive_fu540_spl_defconfig
> @@ -0,0 +1,26 @@
> +CONFIG_RISCV=y
> +CONFIG_ENV_SIZE=0x20000
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_TARGET_SIFIVE_FU540=y
> +CONFIG_ARCH_RV64I=y
> +CONFIG_RISCV_SMODE=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_FIT=y
> +CONFIG_MISC=y
> +CONFIG_EMEMORY_OTP=y
> +CONFIG_MISC_INIT_R=y
> +CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
> +CONFIG_DISPLAY_CPUINFO=y
> +CONFIG_DISPLAY_BOARDINFO=y
> +CONFIG_OF_SEPARATE=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_DM_MTD=y
> +CONFIG_SPL=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SPI_SUPPORT=y
> +CONFIG_SPL_YMODEM_SUPPORT=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=1
> +CONFIG_SPL_CLK=y
> +CONFIG_SPL_PAYLOAD="u-boot.itb"
> diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
> index 2756ed5a77..ef3ae9b650 100644
> --- a/include/configs/sifive-fu540.h
> +++ b/include/configs/sifive-fu540.h
> @@ -11,6 +11,22 @@
>
>  #include <linux/sizes.h>
>
> +#ifdef CONFIG_SPL
> +
> +#define CONFIG_SPL_MAX_SIZE            0x00100000
> +#define CONFIG_SPL_BSS_START_ADDR      0x85000000
> +#define CONFIG_SPL_BSS_MAX_SIZE                0x00100000
> +#define CONFIG_SYS_SPL_MALLOC_START    (CONFIG_SPL_BSS_START_ADDR + \
> +                                        CONFIG_SPL_BSS_MAX_SIZE)
> +#define CONFIG_SYS_SPL_MALLOC_SIZE     0x00100000
> +
> +#define CONFIG_SPL_LOAD_FIT_ADDRESS    0x84000000
> +
> +#define CONFIG_SPL_STACK       (0x08000000 + 0x001D0000 - \
> +                                GENERATED_GBL_DATA_SIZE)
> +
> +#endif
> +
>  #define CONFIG_SYS_SDRAM_BASE          0x80000000
>  #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_SDRAM_BASE + SZ_2M)
>
> @@ -24,6 +40,7 @@
>
>  /* Environment options */
>
> +#ifndef CONFIG_SPL_BUILD
>  #define BOOT_TARGET_DEVICES(func) \
>         func(MMC, mmc, 0) \
>         func(DHCP, dhcp, na)
> @@ -43,5 +60,6 @@
>  #define CONFIG_PREBOOT \
>         "setenv fdt_addr ${fdtcontroladdr};" \
>         "fdt addr ${fdtcontroladdr};"
> +#endif
>
>  #endif /* __CONFIG_H */
> --
> 2.17.1
>

Regards,
Anup
Pragnesh Patel Jan. 20, 2020, 11:16 a.m. UTC | #2 
Hi Anup,

>-----Original Message-----
>From: Anup Patel <anup at brainfault.org>
>Sent: 20 January 2020 11:35
>To: Pragnesh Patel <pragnesh.patel at sifive.com>
>Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Palmer Dabbelt
><palmerdabbelt at google.com>; Atish Patra <atish.patra at wdc.com>; Palmer
>Dabbelt ( Sifive) <palmer at sifive.com>
>Subject: Re: [PATCH v2 8/9] riscv: sifive: fu540: add SPL configuration
>
>On Fri, Jan 17, 2020 at 6:18 PM Pragnesh Patel
><pragnesh.patel at sifive.com> wrote:
>>
>> This patch provides sifive_fu540_spl_defconfig which can support
>> U-boot SPL to boot from L2 LIM (0x0800_0000) and then boot U-boot
>> FIT image including OpenSBI FW_DYNAMIC firmware and U-Boot proper
>> images from MMC boot devices.
>>
>> With sifive_fu540_spl_defconfig:
>>
>> U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
>> u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
>> image u-boot.itb from SD card (replace fw_payload.bin with u-boot.itb)
>> into RAM.
>>
>> SPL related code is leverage from FSBL
>> (https://github.com/sifive/freedom-u540-c000-bootloader.git)
>
>Please look at my comments in PATCH7 regarding patch break-up.
>
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
>> ---
>>  arch/riscv/include/asm/csr.h       |   2 +
>>  board/sifive/fu540/Kconfig         |   8 +
>>  board/sifive/fu540/MAINTAINERS     |   1 +
>>  board/sifive/fu540/Makefile        |   5 +
>>  board/sifive/fu540/ddrregs.c       | 625 +++++++++++++++++++++++++++++
>>  board/sifive/fu540/fu540.c         |  27 +-
>>  board/sifive/fu540/spl.c           | 307 ++++++++++++++
>>  configs/sifive_fu540_spl_defconfig |  26 ++
>>  include/configs/sifive-fu540.h     |  18 +
>>  9 files changed, 1018 insertions(+), 1 deletion(-)
>>  create mode 100644 board/sifive/fu540/ddrregs.c
>>  create mode 100644 board/sifive/fu540/spl.c
>>  create mode 100644 configs/sifive_fu540_spl_defconfig
>>
>> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
>> index d1520743a2..125c05dd8a 100644
>> --- a/arch/riscv/include/asm/csr.h
>> +++ b/arch/riscv/include/asm/csr.h
>> @@ -103,6 +103,8 @@
>>  #define CSR_TIMEH              0xc81
>>  #define CSR_INSTRETH           0xc82
>>  #define CSR_MHARTID            0xf14
>> +#define CSR_MCYCLE             0xb00
>> +#define CSR_MCYCLEH            0xb80
>
>This is a totally unrelated change. Please remove this change OR
>send it as separate patch.

I will remove this in v3, thanks.

>
>>
>>  #ifndef __ASSEMBLY__
>>
>> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
>> index 816a135b21..ac7c6bff37 100644
>> --- a/board/sifive/fu540/Kconfig
>> +++ b/board/sifive/fu540/Kconfig
>> @@ -16,12 +16,20 @@ config SYS_SOC
>>         default "fu540"
>>
>>  config SYS_TEXT_BASE
>> +       default 0x80200000 if SPL
>>         default 0x80000000 if !RISCV_SMODE
>>         default 0x80200000 if RISCV_SMODE
>>
>> +config SPL_TEXT_BASE
>> +       default 0x08000000
>> +
>> +config SPL_OPENSBI_LOAD_ADDR
>> +       default 0x80000000
>> +
>>  config BOARD_SPECIFIC_OPTIONS # dummy
>>         def_bool y
>>         select GENERIC_RISCV
>> +       select SUPPORT_SPL
>>         imply CMD_DHCP
>>         imply CMD_EXT2
>>         imply CMD_EXT4
>> diff --git a/board/sifive/fu540/MAINTAINERS
>b/board/sifive/fu540/MAINTAINERS
>> index 702d803ad8..42c3f3deb0 100644
>> --- a/board/sifive/fu540/MAINTAINERS
>> +++ b/board/sifive/fu540/MAINTAINERS
>> @@ -7,3 +7,4 @@ S:      Maintained
>>  F:     board/sifive/fu540/
>>  F:     include/configs/sifive-fu540.h
>>  F:     configs/sifive_fu540_defconfig
>> +F:     configs/sifive_fu540_spl_defconfig
>
>Palmer's email address is incorrect in this file.
>
>I suggest to have separate patch for updating fu540/MAINTAINERS
>file and not change fu540/MAINTAINERS here:
>1. Add configs/sifive_fu540_spl_defconfig
>2. Update Palmer's email address
>3. Add yourself as first/primary maintainer for sifive/fu540 board support.
>Other folks (including Me and Atish) are busy with other things so they
>we are slow on U-Boot patch reviewes.

Will update fu540/MAINTAINERS and add a separate patch in v3.

>
>> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
>> index 6e1862c475..f01e731913 100644
>> --- a/board/sifive/fu540/Makefile
>> +++ b/board/sifive/fu540/Makefile
>> @@ -3,3 +3,8 @@
>>  # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>>
>>  obj-y  += fu540.o
>> +
>> +ifdef CONFIG_SPL_BUILD
>> +obj-y += spl.o
>> +obj-y += ddrregs.o
>> +endif
>> diff --git a/board/sifive/fu540/ddrregs.c b/board/sifive/fu540/ddrregs.c
>> new file mode 100644
>> index 0000000000..5c9c238aa1
>> --- /dev/null
>> +++ b/board/sifive/fu540/ddrregs.c
>> @@ -0,0 +1,625 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (c) 2019 SiFive, Inc
>> + *
>> + * Authors:
>> + *   Pragnesh Patel <pragnesh.patel at sifive.com>
>> + *   Troy Benjegerdes <troy.benjegerdes at sifive.com>
>> + */
>> +
>> +#include <common.h>
>> +
>> +#include "regconfig-ctl.h"
>> +#include "regconfig-phy.h"
>> +
>> +u32 ddr_phy_settings[1215] = {
>> +       DENALI_PHY_00_DATA, DENALI_PHY_01_DATA,
>DENALI_PHY_02_DATA,
>> +       DENALI_PHY_03_DATA, DENALI_PHY_04_DATA,
>DENALI_PHY_05_DATA,
>> +       DENALI_PHY_06_DATA, DENALI_PHY_07_DATA,
>DENALI_PHY_08_DATA,
>> +       DENALI_PHY_09_DATA,
>> +       DENALI_PHY_10_DATA, DENALI_PHY_11_DATA,
>DENALI_PHY_12_DATA,
>> +       DENALI_PHY_13_DATA, DENALI_PHY_14_DATA,
>DENALI_PHY_15_DATA,
>> +       DENALI_PHY_16_DATA, DENALI_PHY_17_DATA,
>DENALI_PHY_18_DATA,
>> +       DENALI_PHY_19_DATA,
>> +       DENALI_PHY_20_DATA, DENALI_PHY_21_DATA,
>> [....]
>> 2.17.1
>>
>
>Regards,
>Anup
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index d1520743a2..125c05dd8a 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -103,6 +103,8 @@ 
 #define CSR_TIMEH		0xc81
 #define CSR_INSTRETH		0xc82
 #define CSR_MHARTID		0xf14
+#define CSR_MCYCLE		0xb00
+#define CSR_MCYCLEH		0xb80
 
 #ifndef __ASSEMBLY__
 
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 816a135b21..ac7c6bff37 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -16,12 +16,20 @@  config SYS_SOC
 	default "fu540"
 
 config SYS_TEXT_BASE
+	default 0x80200000 if SPL
 	default 0x80000000 if !RISCV_SMODE
 	default 0x80200000 if RISCV_SMODE
 
+config SPL_TEXT_BASE
+	default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x80000000
+
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select GENERIC_RISCV
+	select SUPPORT_SPL
 	imply CMD_DHCP
 	imply CMD_EXT2
 	imply CMD_EXT4
diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS
index 702d803ad8..42c3f3deb0 100644
--- a/board/sifive/fu540/MAINTAINERS
+++ b/board/sifive/fu540/MAINTAINERS
@@ -7,3 +7,4 @@  S:	Maintained
 F:	board/sifive/fu540/
 F:	include/configs/sifive-fu540.h
 F:	configs/sifive_fu540_defconfig
+F:	configs/sifive_fu540_spl_defconfig
diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
index 6e1862c475..f01e731913 100644
--- a/board/sifive/fu540/Makefile
+++ b/board/sifive/fu540/Makefile
@@ -3,3 +3,8 @@ 
 # Copyright (c) 2019 Western Digital Corporation or its affiliates.
 
 obj-y	+= fu540.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += ddrregs.o
+endif
diff --git a/board/sifive/fu540/ddrregs.c b/board/sifive/fu540/ddrregs.c
new file mode 100644
index 0000000000..5c9c238aa1
--- /dev/null
+++ b/board/sifive/fu540/ddrregs.c
@@ -0,0 +1,625 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel at sifive.com>
+ *   Troy Benjegerdes <troy.benjegerdes at sifive.com>
+ */
+
+#include <common.h>
+
+#include "regconfig-ctl.h"
+#include "regconfig-phy.h"
+
+u32 ddr_phy_settings[1215] = {
+	DENALI_PHY_00_DATA, DENALI_PHY_01_DATA, DENALI_PHY_02_DATA,
+	DENALI_PHY_03_DATA, DENALI_PHY_04_DATA, DENALI_PHY_05_DATA,
+	DENALI_PHY_06_DATA, DENALI_PHY_07_DATA, DENALI_PHY_08_DATA,
+	DENALI_PHY_09_DATA,
+	DENALI_PHY_10_DATA, DENALI_PHY_11_DATA, DENALI_PHY_12_DATA,
+	DENALI_PHY_13_DATA, DENALI_PHY_14_DATA, DENALI_PHY_15_DATA,
+	DENALI_PHY_16_DATA, DENALI_PHY_17_DATA, DENALI_PHY_18_DATA,
+	DENALI_PHY_19_DATA,
+	DENALI_PHY_20_DATA, DENALI_PHY_21_DATA, DENALI_PHY_22_DATA,
+	DENALI_PHY_23_DATA, DENALI_PHY_24_DATA, DENALI_PHY_25_DATA,
+	DENALI_PHY_26_DATA, DENALI_PHY_27_DATA, DENALI_PHY_28_DATA,
+	DENALI_PHY_29_DATA,
+	DENALI_PHY_30_DATA, DENALI_PHY_31_DATA, DENALI_PHY_32_DATA,
+	DENALI_PHY_33_DATA, DENALI_PHY_34_DATA, DENALI_PHY_35_DATA,
+	DENALI_PHY_36_DATA, DENALI_PHY_37_DATA, DENALI_PHY_38_DATA,
+	DENALI_PHY_39_DATA,
+	DENALI_PHY_40_DATA, DENALI_PHY_41_DATA, DENALI_PHY_42_DATA,
+	DENALI_PHY_43_DATA, DENALI_PHY_44_DATA, DENALI_PHY_45_DATA,
+	DENALI_PHY_46_DATA, DENALI_PHY_47_DATA, DENALI_PHY_48_DATA,
+	DENALI_PHY_49_DATA,
+	DENALI_PHY_50_DATA, DENALI_PHY_51_DATA, DENALI_PHY_52_DATA,
+	DENALI_PHY_53_DATA, DENALI_PHY_54_DATA, DENALI_PHY_55_DATA,
+	DENALI_PHY_56_DATA, DENALI_PHY_57_DATA, DENALI_PHY_58_DATA,
+	DENALI_PHY_59_DATA,
+	DENALI_PHY_60_DATA, DENALI_PHY_61_DATA, DENALI_PHY_62_DATA,
+	DENALI_PHY_63_DATA, DENALI_PHY_64_DATA, DENALI_PHY_65_DATA,
+	DENALI_PHY_66_DATA, DENALI_PHY_67_DATA, DENALI_PHY_68_DATA,
+	DENALI_PHY_69_DATA,
+	DENALI_PHY_70_DATA, DENALI_PHY_71_DATA, DENALI_PHY_72_DATA,
+	DENALI_PHY_73_DATA, DENALI_PHY_74_DATA, DENALI_PHY_75_DATA,
+	DENALI_PHY_76_DATA, DENALI_PHY_77_DATA, DENALI_PHY_78_DATA,
+	DENALI_PHY_79_DATA,
+	DENALI_PHY_80_DATA, DENALI_PHY_81_DATA, DENALI_PHY_82_DATA,
+	DENALI_PHY_83_DATA, DENALI_PHY_84_DATA, DENALI_PHY_85_DATA,
+	DENALI_PHY_86_DATA, DENALI_PHY_87_DATA, DENALI_PHY_88_DATA,
+	DENALI_PHY_89_DATA,
+	DENALI_PHY_90_DATA, DENALI_PHY_91_DATA, DENALI_PHY_92_DATA,
+	DENALI_PHY_93_DATA, DENALI_PHY_94_DATA, DENALI_PHY_95_DATA,
+	DENALI_PHY_96_DATA, DENALI_PHY_97_DATA, DENALI_PHY_98_DATA,
+	DENALI_PHY_99_DATA,
+
+	DENALI_PHY_100_DATA, DENALI_PHY_101_DATA, DENALI_PHY_102_DATA,
+	DENALI_PHY_103_DATA, DENALI_PHY_104_DATA, DENALI_PHY_105_DATA,
+	DENALI_PHY_106_DATA, DENALI_PHY_107_DATA, DENALI_PHY_108_DATA,
+	DENALI_PHY_109_DATA,
+	DENALI_PHY_110_DATA, DENALI_PHY_111_DATA, DENALI_PHY_112_DATA,
+	DENALI_PHY_113_DATA, DENALI_PHY_114_DATA, DENALI_PHY_115_DATA,
+	DENALI_PHY_116_DATA, DENALI_PHY_117_DATA, DENALI_PHY_118_DATA,
+	DENALI_PHY_119_DATA,
+	DENALI_PHY_120_DATA, DENALI_PHY_121_DATA, DENALI_PHY_122_DATA,
+	DENALI_PHY_123_DATA, DENALI_PHY_124_DATA, DENALI_PHY_125_DATA,
+	DENALI_PHY_126_DATA, DENALI_PHY_127_DATA, DENALI_PHY_128_DATA,
+	DENALI_PHY_129_DATA,
+	DENALI_PHY_130_DATA, DENALI_PHY_131_DATA, DENALI_PHY_132_DATA,
+	DENALI_PHY_133_DATA, DENALI_PHY_134_DATA, DENALI_PHY_135_DATA,
+	DENALI_PHY_136_DATA, DENALI_PHY_137_DATA, DENALI_PHY_138_DATA,
+	DENALI_PHY_139_DATA,
+	DENALI_PHY_140_DATA, DENALI_PHY_141_DATA, DENALI_PHY_142_DATA,
+	DENALI_PHY_143_DATA, DENALI_PHY_144_DATA, DENALI_PHY_145_DATA,
+	DENALI_PHY_146_DATA, DENALI_PHY_147_DATA, DENALI_PHY_148_DATA,
+	DENALI_PHY_149_DATA,
+	DENALI_PHY_150_DATA, DENALI_PHY_151_DATA, DENALI_PHY_152_DATA,
+	DENALI_PHY_153_DATA, DENALI_PHY_154_DATA, DENALI_PHY_155_DATA,
+	DENALI_PHY_156_DATA, DENALI_PHY_157_DATA, DENALI_PHY_158_DATA,
+	DENALI_PHY_159_DATA,
+	DENALI_PHY_160_DATA, DENALI_PHY_161_DATA, DENALI_PHY_162_DATA,
+	DENALI_PHY_163_DATA, DENALI_PHY_164_DATA, DENALI_PHY_165_DATA,
+	DENALI_PHY_166_DATA, DENALI_PHY_167_DATA, DENALI_PHY_168_DATA,
+	DENALI_PHY_169_DATA,
+	DENALI_PHY_170_DATA, DENALI_PHY_171_DATA, DENALI_PHY_172_DATA,
+	DENALI_PHY_173_DATA, DENALI_PHY_174_DATA, DENALI_PHY_175_DATA,
+	DENALI_PHY_176_DATA, DENALI_PHY_177_DATA, DENALI_PHY_178_DATA,
+	DENALI_PHY_179_DATA,
+	DENALI_PHY_180_DATA, DENALI_PHY_181_DATA, DENALI_PHY_182_DATA,
+	DENALI_PHY_183_DATA, DENALI_PHY_184_DATA, DENALI_PHY_185_DATA,
+	DENALI_PHY_186_DATA, DENALI_PHY_187_DATA, DENALI_PHY_188_DATA,
+	DENALI_PHY_189_DATA,
+	DENALI_PHY_190_DATA, DENALI_PHY_191_DATA, DENALI_PHY_192_DATA,
+	DENALI_PHY_193_DATA, DENALI_PHY_194_DATA, DENALI_PHY_195_DATA,
+	DENALI_PHY_196_DATA, DENALI_PHY_197_DATA, DENALI_PHY_198_DATA,
+	DENALI_PHY_199_DATA,
+
+	DENALI_PHY_200_DATA, DENALI_PHY_201_DATA, DENALI_PHY_202_DATA,
+	DENALI_PHY_203_DATA, DENALI_PHY_204_DATA, DENALI_PHY_205_DATA,
+	DENALI_PHY_206_DATA, DENALI_PHY_207_DATA, DENALI_PHY_208_DATA,
+	DENALI_PHY_209_DATA,
+	DENALI_PHY_210_DATA, DENALI_PHY_211_DATA, DENALI_PHY_212_DATA,
+	DENALI_PHY_213_DATA, DENALI_PHY_214_DATA, DENALI_PHY_215_DATA,
+	DENALI_PHY_216_DATA, DENALI_PHY_217_DATA, DENALI_PHY_218_DATA,
+	DENALI_PHY_219_DATA,
+	DENALI_PHY_220_DATA, DENALI_PHY_221_DATA, DENALI_PHY_222_DATA,
+	DENALI_PHY_223_DATA, DENALI_PHY_224_DATA, DENALI_PHY_225_DATA,
+	DENALI_PHY_226_DATA, DENALI_PHY_227_DATA, DENALI_PHY_228_DATA,
+	DENALI_PHY_229_DATA,
+	DENALI_PHY_230_DATA, DENALI_PHY_231_DATA, DENALI_PHY_232_DATA,
+	DENALI_PHY_233_DATA, DENALI_PHY_234_DATA, DENALI_PHY_235_DATA,
+	DENALI_PHY_236_DATA, DENALI_PHY_237_DATA, DENALI_PHY_238_DATA,
+	DENALI_PHY_239_DATA,
+	DENALI_PHY_240_DATA, DENALI_PHY_241_DATA, DENALI_PHY_242_DATA,
+	DENALI_PHY_243_DATA, DENALI_PHY_244_DATA, DENALI_PHY_245_DATA,
+	DENALI_PHY_246_DATA, DENALI_PHY_247_DATA, DENALI_PHY_248_DATA,
+	DENALI_PHY_249_DATA,
+	DENALI_PHY_250_DATA, DENALI_PHY_251_DATA, DENALI_PHY_252_DATA,
+	DENALI_PHY_253_DATA, DENALI_PHY_254_DATA, DENALI_PHY_255_DATA,
+	DENALI_PHY_256_DATA, DENALI_PHY_257_DATA, DENALI_PHY_258_DATA,
+	DENALI_PHY_259_DATA,
+	DENALI_PHY_260_DATA, DENALI_PHY_261_DATA, DENALI_PHY_262_DATA,
+	DENALI_PHY_263_DATA, DENALI_PHY_264_DATA, DENALI_PHY_265_DATA,
+	DENALI_PHY_266_DATA, DENALI_PHY_267_DATA, DENALI_PHY_268_DATA,
+	DENALI_PHY_269_DATA,
+	DENALI_PHY_270_DATA, DENALI_PHY_271_DATA, DENALI_PHY_272_DATA,
+	DENALI_PHY_273_DATA, DENALI_PHY_274_DATA, DENALI_PHY_275_DATA,
+	DENALI_PHY_276_DATA, DENALI_PHY_277_DATA, DENALI_PHY_278_DATA,
+	DENALI_PHY_279_DATA,
+	DENALI_PHY_280_DATA, DENALI_PHY_281_DATA, DENALI_PHY_282_DATA,
+	DENALI_PHY_283_DATA, DENALI_PHY_284_DATA, DENALI_PHY_285_DATA,
+	DENALI_PHY_286_DATA, DENALI_PHY_287_DATA, DENALI_PHY_288_DATA,
+	DENALI_PHY_289_DATA,
+	DENALI_PHY_290_DATA, DENALI_PHY_291_DATA, DENALI_PHY_292_DATA,
+	DENALI_PHY_293_DATA, DENALI_PHY_294_DATA, DENALI_PHY_295_DATA,
+	DENALI_PHY_296_DATA, DENALI_PHY_297_DATA, DENALI_PHY_298_DATA,
+	DENALI_PHY_299_DATA,
+
+	DENALI_PHY_300_DATA, DENALI_PHY_301_DATA, DENALI_PHY_302_DATA,
+	DENALI_PHY_303_DATA, DENALI_PHY_304_DATA, DENALI_PHY_305_DATA,
+	DENALI_PHY_306_DATA, DENALI_PHY_307_DATA, DENALI_PHY_308_DATA,
+	DENALI_PHY_309_DATA,
+	DENALI_PHY_310_DATA, DENALI_PHY_311_DATA, DENALI_PHY_312_DATA,
+	DENALI_PHY_313_DATA, DENALI_PHY_314_DATA, DENALI_PHY_315_DATA,
+	DENALI_PHY_316_DATA, DENALI_PHY_317_DATA, DENALI_PHY_318_DATA,
+	DENALI_PHY_319_DATA,
+	DENALI_PHY_320_DATA, DENALI_PHY_321_DATA, DENALI_PHY_322_DATA,
+	DENALI_PHY_323_DATA, DENALI_PHY_324_DATA, DENALI_PHY_325_DATA,
+	DENALI_PHY_326_DATA, DENALI_PHY_327_DATA, DENALI_PHY_328_DATA,
+	DENALI_PHY_329_DATA,
+	DENALI_PHY_330_DATA, DENALI_PHY_331_DATA, DENALI_PHY_332_DATA,
+	DENALI_PHY_333_DATA, DENALI_PHY_334_DATA, DENALI_PHY_335_DATA,
+	DENALI_PHY_336_DATA, DENALI_PHY_337_DATA, DENALI_PHY_338_DATA,
+	DENALI_PHY_339_DATA,
+	DENALI_PHY_340_DATA, DENALI_PHY_341_DATA, DENALI_PHY_342_DATA,
+	DENALI_PHY_343_DATA, DENALI_PHY_344_DATA, DENALI_PHY_345_DATA,
+	DENALI_PHY_346_DATA, DENALI_PHY_347_DATA, DENALI_PHY_348_DATA,
+	DENALI_PHY_349_DATA,
+	DENALI_PHY_350_DATA, DENALI_PHY_351_DATA, DENALI_PHY_352_DATA,
+	DENALI_PHY_353_DATA, DENALI_PHY_354_DATA, DENALI_PHY_355_DATA,
+	DENALI_PHY_356_DATA, DENALI_PHY_357_DATA, DENALI_PHY_358_DATA,
+	DENALI_PHY_359_DATA,
+	DENALI_PHY_360_DATA, DENALI_PHY_361_DATA, DENALI_PHY_362_DATA,
+	DENALI_PHY_363_DATA, DENALI_PHY_364_DATA, DENALI_PHY_365_DATA,
+	DENALI_PHY_366_DATA, DENALI_PHY_367_DATA, DENALI_PHY_368_DATA,
+	DENALI_PHY_369_DATA,
+	DENALI_PHY_370_DATA, DENALI_PHY_371_DATA, DENALI_PHY_372_DATA,
+	DENALI_PHY_373_DATA, DENALI_PHY_374_DATA, DENALI_PHY_375_DATA,
+	DENALI_PHY_376_DATA, DENALI_PHY_377_DATA, DENALI_PHY_378_DATA,
+	DENALI_PHY_379_DATA,
+	DENALI_PHY_380_DATA, DENALI_PHY_381_DATA, DENALI_PHY_382_DATA,
+	DENALI_PHY_383_DATA, DENALI_PHY_384_DATA, DENALI_PHY_385_DATA,
+	DENALI_PHY_386_DATA, DENALI_PHY_387_DATA, DENALI_PHY_388_DATA,
+	DENALI_PHY_389_DATA,
+	DENALI_PHY_390_DATA, DENALI_PHY_391_DATA, DENALI_PHY_392_DATA,
+	DENALI_PHY_393_DATA, DENALI_PHY_394_DATA, DENALI_PHY_395_DATA,
+	DENALI_PHY_396_DATA, DENALI_PHY_397_DATA, DENALI_PHY_398_DATA,
+	DENALI_PHY_399_DATA,
+
+	DENALI_PHY_400_DATA, DENALI_PHY_401_DATA, DENALI_PHY_402_DATA,
+	DENALI_PHY_403_DATA, DENALI_PHY_404_DATA, DENALI_PHY_405_DATA,
+	DENALI_PHY_406_DATA, DENALI_PHY_407_DATA, DENALI_PHY_408_DATA,
+	DENALI_PHY_409_DATA,
+	DENALI_PHY_410_DATA, DENALI_PHY_411_DATA, DENALI_PHY_412_DATA,
+	DENALI_PHY_413_DATA, DENALI_PHY_414_DATA, DENALI_PHY_415_DATA,
+	DENALI_PHY_416_DATA, DENALI_PHY_417_DATA, DENALI_PHY_418_DATA,
+	DENALI_PHY_419_DATA,
+	DENALI_PHY_420_DATA, DENALI_PHY_421_DATA, DENALI_PHY_422_DATA,
+	DENALI_PHY_423_DATA, DENALI_PHY_424_DATA, DENALI_PHY_425_DATA,
+	DENALI_PHY_426_DATA, DENALI_PHY_427_DATA, DENALI_PHY_428_DATA,
+	DENALI_PHY_429_DATA,
+	DENALI_PHY_430_DATA, DENALI_PHY_431_DATA, DENALI_PHY_432_DATA,
+	DENALI_PHY_433_DATA, DENALI_PHY_434_DATA, DENALI_PHY_435_DATA,
+	DENALI_PHY_436_DATA, DENALI_PHY_437_DATA, DENALI_PHY_438_DATA,
+	DENALI_PHY_439_DATA,
+	DENALI_PHY_440_DATA, DENALI_PHY_441_DATA, DENALI_PHY_442_DATA,
+	DENALI_PHY_443_DATA, DENALI_PHY_444_DATA, DENALI_PHY_445_DATA,
+	DENALI_PHY_446_DATA, DENALI_PHY_447_DATA, DENALI_PHY_448_DATA,
+	DENALI_PHY_449_DATA,
+	DENALI_PHY_450_DATA, DENALI_PHY_451_DATA, DENALI_PHY_452_DATA,
+	DENALI_PHY_453_DATA, DENALI_PHY_454_DATA, DENALI_PHY_455_DATA,
+	DENALI_PHY_456_DATA, DENALI_PHY_457_DATA, DENALI_PHY_458_DATA,
+	DENALI_PHY_459_DATA,
+	DENALI_PHY_460_DATA, DENALI_PHY_461_DATA, DENALI_PHY_462_DATA,
+	DENALI_PHY_463_DATA, DENALI_PHY_464_DATA, DENALI_PHY_465_DATA,
+	DENALI_PHY_466_DATA, DENALI_PHY_467_DATA, DENALI_PHY_468_DATA,
+	DENALI_PHY_469_DATA,
+	DENALI_PHY_470_DATA, DENALI_PHY_471_DATA, DENALI_PHY_472_DATA,
+	DENALI_PHY_473_DATA, DENALI_PHY_474_DATA, DENALI_PHY_475_DATA,
+	DENALI_PHY_476_DATA, DENALI_PHY_477_DATA, DENALI_PHY_478_DATA,
+	DENALI_PHY_479_DATA,
+	DENALI_PHY_480_DATA, DENALI_PHY_481_DATA, DENALI_PHY_482_DATA,
+	DENALI_PHY_483_DATA, DENALI_PHY_484_DATA, DENALI_PHY_485_DATA,
+	DENALI_PHY_486_DATA, DENALI_PHY_487_DATA, DENALI_PHY_488_DATA,
+	DENALI_PHY_489_DATA,
+	DENALI_PHY_490_DATA, DENALI_PHY_491_DATA, DENALI_PHY_492_DATA,
+	DENALI_PHY_493_DATA, DENALI_PHY_494_DATA, DENALI_PHY_495_DATA,
+	DENALI_PHY_496_DATA, DENALI_PHY_497_DATA, DENALI_PHY_498_DATA,
+	DENALI_PHY_499_DATA,
+
+	DENALI_PHY_500_DATA, DENALI_PHY_501_DATA, DENALI_PHY_502_DATA,
+	DENALI_PHY_503_DATA, DENALI_PHY_504_DATA, DENALI_PHY_505_DATA,
+	DENALI_PHY_506_DATA, DENALI_PHY_507_DATA, DENALI_PHY_508_DATA,
+	DENALI_PHY_509_DATA,
+	DENALI_PHY_510_DATA, DENALI_PHY_511_DATA, DENALI_PHY_512_DATA,
+	DENALI_PHY_513_DATA, DENALI_PHY_514_DATA, DENALI_PHY_515_DATA,
+	DENALI_PHY_516_DATA, DENALI_PHY_517_DATA, DENALI_PHY_518_DATA,
+	DENALI_PHY_519_DATA,
+	DENALI_PHY_520_DATA, DENALI_PHY_521_DATA, DENALI_PHY_522_DATA,
+	DENALI_PHY_523_DATA, DENALI_PHY_524_DATA, DENALI_PHY_525_DATA,
+	DENALI_PHY_526_DATA, DENALI_PHY_527_DATA, DENALI_PHY_528_DATA,
+	DENALI_PHY_529_DATA,
+	DENALI_PHY_530_DATA, DENALI_PHY_531_DATA, DENALI_PHY_532_DATA,
+	DENALI_PHY_533_DATA, DENALI_PHY_534_DATA, DENALI_PHY_535_DATA,
+	DENALI_PHY_536_DATA, DENALI_PHY_537_DATA, DENALI_PHY_538_DATA,
+	DENALI_PHY_539_DATA,
+	DENALI_PHY_540_DATA, DENALI_PHY_541_DATA, DENALI_PHY_542_DATA,
+	DENALI_PHY_543_DATA, DENALI_PHY_544_DATA, DENALI_PHY_545_DATA,
+	DENALI_PHY_546_DATA, DENALI_PHY_547_DATA, DENALI_PHY_548_DATA,
+	DENALI_PHY_549_DATA,
+	DENALI_PHY_550_DATA, DENALI_PHY_551_DATA, DENALI_PHY_552_DATA,
+	DENALI_PHY_553_DATA, DENALI_PHY_554_DATA, DENALI_PHY_555_DATA,
+	DENALI_PHY_556_DATA, DENALI_PHY_557_DATA, DENALI_PHY_558_DATA,
+	DENALI_PHY_559_DATA,
+	DENALI_PHY_560_DATA, DENALI_PHY_561_DATA, DENALI_PHY_562_DATA,
+	DENALI_PHY_563_DATA, DENALI_PHY_564_DATA, DENALI_PHY_565_DATA,
+	DENALI_PHY_566_DATA, DENALI_PHY_567_DATA, DENALI_PHY_568_DATA,
+	DENALI_PHY_569_DATA,
+	DENALI_PHY_570_DATA, DENALI_PHY_571_DATA, DENALI_PHY_572_DATA,
+	DENALI_PHY_573_DATA, DENALI_PHY_574_DATA, DENALI_PHY_575_DATA,
+	DENALI_PHY_576_DATA, DENALI_PHY_577_DATA, DENALI_PHY_578_DATA,
+	DENALI_PHY_579_DATA,
+	DENALI_PHY_580_DATA, DENALI_PHY_581_DATA, DENALI_PHY_582_DATA,
+	DENALI_PHY_583_DATA, DENALI_PHY_584_DATA, DENALI_PHY_585_DATA,
+	DENALI_PHY_586_DATA, DENALI_PHY_587_DATA, DENALI_PHY_588_DATA,
+	DENALI_PHY_589_DATA,
+	DENALI_PHY_590_DATA, DENALI_PHY_591_DATA, DENALI_PHY_592_DATA,
+	DENALI_PHY_593_DATA, DENALI_PHY_594_DATA, DENALI_PHY_595_DATA,
+	DENALI_PHY_596_DATA, DENALI_PHY_597_DATA, DENALI_PHY_598_DATA,
+	DENALI_PHY_599_DATA,
+
+	DENALI_PHY_600_DATA, DENALI_PHY_601_DATA, DENALI_PHY_602_DATA,
+	DENALI_PHY_603_DATA, DENALI_PHY_604_DATA, DENALI_PHY_605_DATA,
+	DENALI_PHY_606_DATA, DENALI_PHY_607_DATA, DENALI_PHY_608_DATA,
+	DENALI_PHY_609_DATA,
+	DENALI_PHY_610_DATA, DENALI_PHY_611_DATA, DENALI_PHY_612_DATA,
+	DENALI_PHY_613_DATA, DENALI_PHY_614_DATA, DENALI_PHY_615_DATA,
+	DENALI_PHY_616_DATA, DENALI_PHY_617_DATA, DENALI_PHY_618_DATA,
+	DENALI_PHY_619_DATA,
+	DENALI_PHY_620_DATA, DENALI_PHY_621_DATA, DENALI_PHY_622_DATA,
+	DENALI_PHY_623_DATA, DENALI_PHY_624_DATA, DENALI_PHY_625_DATA,
+	DENALI_PHY_626_DATA, DENALI_PHY_627_DATA, DENALI_PHY_628_DATA,
+	DENALI_PHY_629_DATA,
+	DENALI_PHY_630_DATA, DENALI_PHY_631_DATA, DENALI_PHY_632_DATA,
+	DENALI_PHY_633_DATA, DENALI_PHY_634_DATA, DENALI_PHY_635_DATA,
+	DENALI_PHY_636_DATA, DENALI_PHY_637_DATA, DENALI_PHY_638_DATA,
+	DENALI_PHY_639_DATA,
+	DENALI_PHY_640_DATA, DENALI_PHY_641_DATA, DENALI_PHY_642_DATA,
+	DENALI_PHY_643_DATA, DENALI_PHY_644_DATA, DENALI_PHY_645_DATA,
+	DENALI_PHY_646_DATA, DENALI_PHY_647_DATA, DENALI_PHY_648_DATA,
+	DENALI_PHY_649_DATA,
+	DENALI_PHY_650_DATA, DENALI_PHY_651_DATA, DENALI_PHY_652_DATA,
+	DENALI_PHY_653_DATA, DENALI_PHY_654_DATA, DENALI_PHY_655_DATA,
+	DENALI_PHY_656_DATA, DENALI_PHY_657_DATA, DENALI_PHY_658_DATA,
+	DENALI_PHY_659_DATA,
+	DENALI_PHY_660_DATA, DENALI_PHY_661_DATA, DENALI_PHY_662_DATA,
+	DENALI_PHY_663_DATA, DENALI_PHY_664_DATA, DENALI_PHY_665_DATA,
+	DENALI_PHY_666_DATA, DENALI_PHY_667_DATA, DENALI_PHY_668_DATA,
+	DENALI_PHY_669_DATA,
+	DENALI_PHY_670_DATA, DENALI_PHY_671_DATA, DENALI_PHY_672_DATA,
+	DENALI_PHY_673_DATA, DENALI_PHY_674_DATA, DENALI_PHY_675_DATA,
+	DENALI_PHY_676_DATA, DENALI_PHY_677_DATA, DENALI_PHY_678_DATA,
+	DENALI_PHY_679_DATA,
+	DENALI_PHY_680_DATA, DENALI_PHY_681_DATA, DENALI_PHY_682_DATA,
+	DENALI_PHY_683_DATA, DENALI_PHY_684_DATA, DENALI_PHY_685_DATA,
+	DENALI_PHY_686_DATA, DENALI_PHY_687_DATA, DENALI_PHY_688_DATA,
+	DENALI_PHY_689_DATA,
+	DENALI_PHY_690_DATA, DENALI_PHY_691_DATA, DENALI_PHY_692_DATA,
+	DENALI_PHY_693_DATA, DENALI_PHY_694_DATA, DENALI_PHY_695_DATA,
+	DENALI_PHY_696_DATA, DENALI_PHY_697_DATA, DENALI_PHY_698_DATA,
+	DENALI_PHY_699_DATA,
+
+	DENALI_PHY_700_DATA, DENALI_PHY_701_DATA, DENALI_PHY_702_DATA,
+	DENALI_PHY_703_DATA, DENALI_PHY_704_DATA, DENALI_PHY_705_DATA,
+	DENALI_PHY_706_DATA, DENALI_PHY_707_DATA, DENALI_PHY_708_DATA,
+	DENALI_PHY_709_DATA,
+	DENALI_PHY_710_DATA, DENALI_PHY_711_DATA, DENALI_PHY_712_DATA,
+	DENALI_PHY_713_DATA, DENALI_PHY_714_DATA, DENALI_PHY_715_DATA,
+	DENALI_PHY_716_DATA, DENALI_PHY_717_DATA, DENALI_PHY_718_DATA,
+	DENALI_PHY_719_DATA,
+	DENALI_PHY_720_DATA, DENALI_PHY_721_DATA, DENALI_PHY_722_DATA,
+	DENALI_PHY_723_DATA, DENALI_PHY_724_DATA, DENALI_PHY_725_DATA,
+	DENALI_PHY_726_DATA, DENALI_PHY_727_DATA, DENALI_PHY_728_DATA,
+	DENALI_PHY_729_DATA,
+	DENALI_PHY_730_DATA, DENALI_PHY_731_DATA, DENALI_PHY_732_DATA,
+	DENALI_PHY_733_DATA, DENALI_PHY_734_DATA, DENALI_PHY_735_DATA,
+	DENALI_PHY_736_DATA, DENALI_PHY_737_DATA, DENALI_PHY_738_DATA,
+	DENALI_PHY_739_DATA,
+	DENALI_PHY_740_DATA, DENALI_PHY_741_DATA, DENALI_PHY_742_DATA,
+	DENALI_PHY_743_DATA, DENALI_PHY_744_DATA, DENALI_PHY_745_DATA,
+	DENALI_PHY_746_DATA, DENALI_PHY_747_DATA, DENALI_PHY_748_DATA,
+	DENALI_PHY_749_DATA,
+	DENALI_PHY_750_DATA, DENALI_PHY_751_DATA, DENALI_PHY_752_DATA,
+	DENALI_PHY_753_DATA, DENALI_PHY_754_DATA, DENALI_PHY_755_DATA,
+	DENALI_PHY_756_DATA, DENALI_PHY_757_DATA, DENALI_PHY_758_DATA,
+	DENALI_PHY_759_DATA,
+	DENALI_PHY_760_DATA, DENALI_PHY_761_DATA, DENALI_PHY_762_DATA,
+	DENALI_PHY_763_DATA, DENALI_PHY_764_DATA, DENALI_PHY_765_DATA,
+	DENALI_PHY_766_DATA, DENALI_PHY_767_DATA, DENALI_PHY_768_DATA,
+	DENALI_PHY_769_DATA,
+	DENALI_PHY_770_DATA, DENALI_PHY_771_DATA, DENALI_PHY_772_DATA,
+	DENALI_PHY_773_DATA, DENALI_PHY_774_DATA, DENALI_PHY_775_DATA,
+	DENALI_PHY_776_DATA, DENALI_PHY_777_DATA, DENALI_PHY_778_DATA,
+	DENALI_PHY_779_DATA,
+	DENALI_PHY_780_DATA, DENALI_PHY_781_DATA, DENALI_PHY_782_DATA,
+	DENALI_PHY_783_DATA, DENALI_PHY_784_DATA, DENALI_PHY_785_DATA,
+	DENALI_PHY_786_DATA, DENALI_PHY_787_DATA, DENALI_PHY_788_DATA,
+	DENALI_PHY_789_DATA,
+	DENALI_PHY_790_DATA, DENALI_PHY_791_DATA, DENALI_PHY_792_DATA,
+	DENALI_PHY_793_DATA, DENALI_PHY_794_DATA, DENALI_PHY_795_DATA,
+	DENALI_PHY_796_DATA, DENALI_PHY_797_DATA, DENALI_PHY_798_DATA,
+	DENALI_PHY_799_DATA,
+
+	DENALI_PHY_800_DATA, DENALI_PHY_801_DATA, DENALI_PHY_802_DATA,
+	DENALI_PHY_803_DATA, DENALI_PHY_804_DATA, DENALI_PHY_805_DATA,
+	DENALI_PHY_806_DATA, DENALI_PHY_807_DATA, DENALI_PHY_808_DATA,
+	DENALI_PHY_809_DATA,
+	DENALI_PHY_810_DATA, DENALI_PHY_811_DATA, DENALI_PHY_812_DATA,
+	DENALI_PHY_813_DATA, DENALI_PHY_814_DATA, DENALI_PHY_815_DATA,
+	DENALI_PHY_816_DATA, DENALI_PHY_817_DATA, DENALI_PHY_818_DATA,
+	DENALI_PHY_819_DATA,
+	DENALI_PHY_820_DATA, DENALI_PHY_821_DATA, DENALI_PHY_822_DATA,
+	DENALI_PHY_823_DATA, DENALI_PHY_824_DATA, DENALI_PHY_825_DATA,
+	DENALI_PHY_826_DATA, DENALI_PHY_827_DATA, DENALI_PHY_828_DATA,
+	DENALI_PHY_829_DATA,
+	DENALI_PHY_830_DATA, DENALI_PHY_831_DATA, DENALI_PHY_832_DATA,
+	DENALI_PHY_833_DATA, DENALI_PHY_834_DATA, DENALI_PHY_835_DATA,
+	DENALI_PHY_836_DATA, DENALI_PHY_837_DATA, DENALI_PHY_838_DATA,
+	DENALI_PHY_839_DATA,
+	DENALI_PHY_840_DATA, DENALI_PHY_841_DATA, DENALI_PHY_842_DATA,
+	DENALI_PHY_843_DATA, DENALI_PHY_844_DATA, DENALI_PHY_845_DATA,
+	DENALI_PHY_846_DATA, DENALI_PHY_847_DATA, DENALI_PHY_848_DATA,
+	DENALI_PHY_849_DATA,
+	DENALI_PHY_850_DATA, DENALI_PHY_851_DATA, DENALI_PHY_852_DATA,
+	DENALI_PHY_853_DATA, DENALI_PHY_854_DATA, DENALI_PHY_855_DATA,
+	DENALI_PHY_856_DATA, DENALI_PHY_857_DATA, DENALI_PHY_858_DATA,
+	DENALI_PHY_859_DATA,
+	DENALI_PHY_860_DATA, DENALI_PHY_861_DATA, DENALI_PHY_862_DATA,
+	DENALI_PHY_863_DATA, DENALI_PHY_864_DATA, DENALI_PHY_865_DATA,
+	DENALI_PHY_866_DATA, DENALI_PHY_867_DATA, DENALI_PHY_868_DATA,
+	DENALI_PHY_869_DATA,
+	DENALI_PHY_870_DATA, DENALI_PHY_871_DATA, DENALI_PHY_872_DATA,
+	DENALI_PHY_873_DATA, DENALI_PHY_874_DATA, DENALI_PHY_875_DATA,
+	DENALI_PHY_876_DATA, DENALI_PHY_877_DATA, DENALI_PHY_878_DATA,
+	DENALI_PHY_879_DATA,
+	DENALI_PHY_880_DATA, DENALI_PHY_881_DATA, DENALI_PHY_882_DATA,
+	DENALI_PHY_883_DATA, DENALI_PHY_884_DATA, DENALI_PHY_885_DATA,
+	DENALI_PHY_886_DATA, DENALI_PHY_887_DATA, DENALI_PHY_888_DATA,
+	DENALI_PHY_889_DATA,
+	DENALI_PHY_890_DATA, DENALI_PHY_891_DATA, DENALI_PHY_892_DATA,
+	DENALI_PHY_893_DATA, DENALI_PHY_894_DATA, DENALI_PHY_895_DATA,
+	DENALI_PHY_896_DATA, DENALI_PHY_897_DATA, DENALI_PHY_898_DATA,
+	DENALI_PHY_899_DATA,
+
+	DENALI_PHY_900_DATA, DENALI_PHY_901_DATA, DENALI_PHY_902_DATA,
+	DENALI_PHY_903_DATA, DENALI_PHY_904_DATA, DENALI_PHY_905_DATA,
+	DENALI_PHY_906_DATA, DENALI_PHY_907_DATA, DENALI_PHY_908_DATA,
+	DENALI_PHY_909_DATA,
+	DENALI_PHY_910_DATA, DENALI_PHY_911_DATA, DENALI_PHY_912_DATA,
+	DENALI_PHY_913_DATA, DENALI_PHY_914_DATA, DENALI_PHY_915_DATA,
+	DENALI_PHY_916_DATA, DENALI_PHY_917_DATA, DENALI_PHY_918_DATA,
+	DENALI_PHY_919_DATA,
+	DENALI_PHY_920_DATA, DENALI_PHY_921_DATA, DENALI_PHY_922_DATA,
+	DENALI_PHY_923_DATA, DENALI_PHY_924_DATA, DENALI_PHY_925_DATA,
+	DENALI_PHY_926_DATA, DENALI_PHY_927_DATA, DENALI_PHY_928_DATA,
+	DENALI_PHY_929_DATA,
+	DENALI_PHY_930_DATA, DENALI_PHY_931_DATA, DENALI_PHY_932_DATA,
+	DENALI_PHY_933_DATA, DENALI_PHY_934_DATA, DENALI_PHY_935_DATA,
+	DENALI_PHY_936_DATA, DENALI_PHY_937_DATA, DENALI_PHY_938_DATA,
+	DENALI_PHY_939_DATA,
+	DENALI_PHY_940_DATA, DENALI_PHY_941_DATA, DENALI_PHY_942_DATA,
+	DENALI_PHY_943_DATA, DENALI_PHY_944_DATA, DENALI_PHY_945_DATA,
+	DENALI_PHY_946_DATA, DENALI_PHY_947_DATA, DENALI_PHY_948_DATA,
+	DENALI_PHY_949_DATA,
+	DENALI_PHY_950_DATA, DENALI_PHY_951_DATA, DENALI_PHY_952_DATA,
+	DENALI_PHY_953_DATA, DENALI_PHY_954_DATA, DENALI_PHY_955_DATA,
+	DENALI_PHY_956_DATA, DENALI_PHY_957_DATA, DENALI_PHY_958_DATA,
+	DENALI_PHY_959_DATA,
+	DENALI_PHY_960_DATA, DENALI_PHY_961_DATA, DENALI_PHY_962_DATA,
+	DENALI_PHY_963_DATA, DENALI_PHY_964_DATA, DENALI_PHY_965_DATA,
+	DENALI_PHY_966_DATA, DENALI_PHY_967_DATA, DENALI_PHY_968_DATA,
+	DENALI_PHY_969_DATA,
+	DENALI_PHY_970_DATA, DENALI_PHY_971_DATA, DENALI_PHY_972_DATA,
+	DENALI_PHY_973_DATA, DENALI_PHY_974_DATA, DENALI_PHY_975_DATA,
+	DENALI_PHY_976_DATA, DENALI_PHY_977_DATA, DENALI_PHY_978_DATA,
+	DENALI_PHY_979_DATA,
+	DENALI_PHY_980_DATA, DENALI_PHY_981_DATA, DENALI_PHY_982_DATA,
+	DENALI_PHY_983_DATA, DENALI_PHY_984_DATA, DENALI_PHY_985_DATA,
+	DENALI_PHY_986_DATA, DENALI_PHY_987_DATA, DENALI_PHY_988_DATA,
+	DENALI_PHY_989_DATA,
+	DENALI_PHY_990_DATA, DENALI_PHY_991_DATA, DENALI_PHY_992_DATA,
+	DENALI_PHY_993_DATA, DENALI_PHY_994_DATA, DENALI_PHY_995_DATA,
+	DENALI_PHY_996_DATA, DENALI_PHY_997_DATA, DENALI_PHY_998_DATA,
+	DENALI_PHY_999_DATA,
+
+	DENALI_PHY_1000_DATA, DENALI_PHY_1001_DATA, DENALI_PHY_1002_DATA,
+	DENALI_PHY_1003_DATA, DENALI_PHY_1004_DATA, DENALI_PHY_1005_DATA,
+	DENALI_PHY_1006_DATA, DENALI_PHY_1007_DATA, DENALI_PHY_1008_DATA,
+	DENALI_PHY_1009_DATA,
+	DENALI_PHY_1010_DATA, DENALI_PHY_1011_DATA, DENALI_PHY_1012_DATA,
+	DENALI_PHY_1013_DATA, DENALI_PHY_1014_DATA, DENALI_PHY_1015_DATA,
+	DENALI_PHY_1016_DATA, DENALI_PHY_1017_DATA, DENALI_PHY_1018_DATA,
+	DENALI_PHY_1019_DATA,
+	DENALI_PHY_1020_DATA, DENALI_PHY_1021_DATA, DENALI_PHY_1022_DATA,
+	DENALI_PHY_1023_DATA, DENALI_PHY_1024_DATA, DENALI_PHY_1025_DATA,
+	DENALI_PHY_1026_DATA, DENALI_PHY_1027_DATA, DENALI_PHY_1028_DATA,
+	DENALI_PHY_1029_DATA,
+	DENALI_PHY_1030_DATA, DENALI_PHY_1031_DATA, DENALI_PHY_1032_DATA,
+	DENALI_PHY_1033_DATA, DENALI_PHY_1034_DATA, DENALI_PHY_1035_DATA,
+	DENALI_PHY_1036_DATA, DENALI_PHY_1037_DATA, DENALI_PHY_1038_DATA,
+	DENALI_PHY_1039_DATA,
+	DENALI_PHY_1040_DATA, DENALI_PHY_1041_DATA, DENALI_PHY_1042_DATA,
+	DENALI_PHY_1043_DATA, DENALI_PHY_1044_DATA, DENALI_PHY_1045_DATA,
+	DENALI_PHY_1046_DATA, DENALI_PHY_1047_DATA, DENALI_PHY_1048_DATA,
+	DENALI_PHY_1049_DATA,
+	DENALI_PHY_1050_DATA, DENALI_PHY_1051_DATA, DENALI_PHY_1052_DATA,
+	DENALI_PHY_1053_DATA, DENALI_PHY_1054_DATA, DENALI_PHY_1055_DATA,
+	DENALI_PHY_1056_DATA, DENALI_PHY_1057_DATA, DENALI_PHY_1058_DATA,
+	DENALI_PHY_1059_DATA,
+	DENALI_PHY_1060_DATA, DENALI_PHY_1061_DATA, DENALI_PHY_1062_DATA,
+	DENALI_PHY_1063_DATA, DENALI_PHY_1064_DATA, DENALI_PHY_1065_DATA,
+	DENALI_PHY_1066_DATA, DENALI_PHY_1067_DATA, DENALI_PHY_1068_DATA,
+	DENALI_PHY_1069_DATA,
+	DENALI_PHY_1070_DATA, DENALI_PHY_1071_DATA, DENALI_PHY_1072_DATA,
+	DENALI_PHY_1073_DATA, DENALI_PHY_1074_DATA, DENALI_PHY_1075_DATA,
+	DENALI_PHY_1076_DATA, DENALI_PHY_1077_DATA, DENALI_PHY_1078_DATA,
+	DENALI_PHY_1079_DATA,
+	DENALI_PHY_1080_DATA, DENALI_PHY_1081_DATA, DENALI_PHY_1082_DATA,
+	DENALI_PHY_1083_DATA, DENALI_PHY_1084_DATA, DENALI_PHY_1085_DATA,
+	DENALI_PHY_1086_DATA, DENALI_PHY_1087_DATA, DENALI_PHY_1088_DATA,
+	DENALI_PHY_1089_DATA,
+	DENALI_PHY_1090_DATA, DENALI_PHY_1091_DATA, DENALI_PHY_1092_DATA,
+	DENALI_PHY_1093_DATA, DENALI_PHY_1094_DATA, DENALI_PHY_1095_DATA,
+	DENALI_PHY_1096_DATA, DENALI_PHY_1097_DATA, DENALI_PHY_1098_DATA,
+	DENALI_PHY_1099_DATA,
+
+	DENALI_PHY_1100_DATA, DENALI_PHY_1101_DATA, DENALI_PHY_1102_DATA,
+	DENALI_PHY_1103_DATA, DENALI_PHY_1104_DATA, DENALI_PHY_1105_DATA,
+	DENALI_PHY_1106_DATA, DENALI_PHY_1107_DATA, DENALI_PHY_1108_DATA,
+	DENALI_PHY_1109_DATA,
+	DENALI_PHY_1110_DATA, DENALI_PHY_1111_DATA, DENALI_PHY_1112_DATA,
+	DENALI_PHY_1113_DATA, DENALI_PHY_1114_DATA, DENALI_PHY_1115_DATA,
+	DENALI_PHY_1116_DATA, DENALI_PHY_1117_DATA, DENALI_PHY_1118_DATA,
+	DENALI_PHY_1119_DATA,
+	DENALI_PHY_1120_DATA, DENALI_PHY_1121_DATA, DENALI_PHY_1122_DATA,
+	DENALI_PHY_1123_DATA, DENALI_PHY_1124_DATA, DENALI_PHY_1125_DATA,
+	DENALI_PHY_1126_DATA, DENALI_PHY_1127_DATA, DENALI_PHY_1128_DATA,
+	DENALI_PHY_1129_DATA,
+	DENALI_PHY_1130_DATA, DENALI_PHY_1131_DATA, DENALI_PHY_1132_DATA,
+	DENALI_PHY_1133_DATA, DENALI_PHY_1134_DATA, DENALI_PHY_1135_DATA,
+	DENALI_PHY_1136_DATA, DENALI_PHY_1137_DATA, DENALI_PHY_1138_DATA,
+	DENALI_PHY_1139_DATA,
+	DENALI_PHY_1140_DATA, DENALI_PHY_1141_DATA, DENALI_PHY_1142_DATA,
+	DENALI_PHY_1143_DATA, DENALI_PHY_1144_DATA, DENALI_PHY_1145_DATA,
+	DENALI_PHY_1146_DATA, DENALI_PHY_1147_DATA, DENALI_PHY_1148_DATA,
+	DENALI_PHY_1149_DATA,
+	DENALI_PHY_1150_DATA, DENALI_PHY_1151_DATA, DENALI_PHY_1152_DATA,
+	DENALI_PHY_1153_DATA, DENALI_PHY_1154_DATA, DENALI_PHY_1155_DATA,
+	DENALI_PHY_1156_DATA, DENALI_PHY_1157_DATA, DENALI_PHY_1158_DATA,
+	DENALI_PHY_1159_DATA,
+	DENALI_PHY_1160_DATA, DENALI_PHY_1161_DATA, DENALI_PHY_1162_DATA,
+	DENALI_PHY_1163_DATA, DENALI_PHY_1164_DATA, DENALI_PHY_1165_DATA,
+	DENALI_PHY_1166_DATA, DENALI_PHY_1167_DATA, DENALI_PHY_1168_DATA,
+	DENALI_PHY_1169_DATA,
+	DENALI_PHY_1170_DATA, DENALI_PHY_1171_DATA, DENALI_PHY_1172_DATA,
+	DENALI_PHY_1173_DATA, DENALI_PHY_1174_DATA, DENALI_PHY_1175_DATA,
+	DENALI_PHY_1176_DATA, DENALI_PHY_1177_DATA, DENALI_PHY_1178_DATA,
+	DENALI_PHY_1179_DATA,
+	DENALI_PHY_1180_DATA, DENALI_PHY_1181_DATA, DENALI_PHY_1182_DATA,
+	DENALI_PHY_1183_DATA, DENALI_PHY_1184_DATA, DENALI_PHY_1185_DATA,
+	DENALI_PHY_1186_DATA, DENALI_PHY_1187_DATA, DENALI_PHY_1188_DATA,
+	DENALI_PHY_1189_DATA,
+	DENALI_PHY_1190_DATA, DENALI_PHY_1191_DATA, DENALI_PHY_1192_DATA,
+	DENALI_PHY_1193_DATA, DENALI_PHY_1194_DATA, DENALI_PHY_1195_DATA,
+	DENALI_PHY_1196_DATA, DENALI_PHY_1197_DATA, DENALI_PHY_1198_DATA,
+	DENALI_PHY_1199_DATA,
+
+	DENALI_PHY_1200_DATA, DENALI_PHY_1201_DATA, DENALI_PHY_1202_DATA,
+	DENALI_PHY_1203_DATA, DENALI_PHY_1204_DATA, DENALI_PHY_1205_DATA,
+	DENALI_PHY_1206_DATA, DENALI_PHY_1207_DATA, DENALI_PHY_1208_DATA,
+	DENALI_PHY_1209_DATA,
+	DENALI_PHY_1210_DATA, DENALI_PHY_1211_DATA, DENALI_PHY_1212_DATA,
+	DENALI_PHY_1213_DATA, DENALI_PHY_1214_DATA
+};
+
+u32 ddr_ctl_settings[265] = {
+	DENALI_CTL_00_DATA, DENALI_CTL_01_DATA, DENALI_CTL_02_DATA,
+	DENALI_CTL_03_DATA, DENALI_CTL_04_DATA, DENALI_CTL_05_DATA,
+	DENALI_CTL_06_DATA, DENALI_CTL_07_DATA, DENALI_CTL_08_DATA,
+	DENALI_CTL_09_DATA,
+	DENALI_CTL_10_DATA, DENALI_CTL_11_DATA, DENALI_CTL_12_DATA,
+	DENALI_CTL_13_DATA, DENALI_CTL_14_DATA, DENALI_CTL_15_DATA,
+	DENALI_CTL_16_DATA, DENALI_CTL_17_DATA, DENALI_CTL_18_DATA,
+	DENALI_CTL_19_DATA,
+	DENALI_CTL_20_DATA, DENALI_CTL_21_DATA, DENALI_CTL_22_DATA,
+	DENALI_CTL_23_DATA, DENALI_CTL_24_DATA, DENALI_CTL_25_DATA,
+	DENALI_CTL_26_DATA, DENALI_CTL_27_DATA, DENALI_CTL_28_DATA,
+	DENALI_CTL_29_DATA,
+	DENALI_CTL_30_DATA, DENALI_CTL_31_DATA, DENALI_CTL_32_DATA,
+	DENALI_CTL_33_DATA, DENALI_CTL_34_DATA, DENALI_CTL_35_DATA,
+	DENALI_CTL_36_DATA, DENALI_CTL_37_DATA, DENALI_CTL_38_DATA,
+	DENALI_CTL_39_DATA,
+	DENALI_CTL_40_DATA, DENALI_CTL_41_DATA, DENALI_CTL_42_DATA,
+	DENALI_CTL_43_DATA, DENALI_CTL_44_DATA, DENALI_CTL_45_DATA,
+	DENALI_CTL_46_DATA, DENALI_CTL_47_DATA, DENALI_CTL_48_DATA,
+	DENALI_CTL_49_DATA,
+	DENALI_CTL_50_DATA, DENALI_CTL_51_DATA, DENALI_CTL_52_DATA,
+	DENALI_CTL_53_DATA, DENALI_CTL_54_DATA, DENALI_CTL_55_DATA,
+	DENALI_CTL_56_DATA, DENALI_CTL_57_DATA, DENALI_CTL_58_DATA,
+	DENALI_CTL_59_DATA,
+	DENALI_CTL_60_DATA, DENALI_CTL_61_DATA, DENALI_CTL_62_DATA,
+	DENALI_CTL_63_DATA, DENALI_CTL_64_DATA, DENALI_CTL_65_DATA,
+	DENALI_CTL_66_DATA, DENALI_CTL_67_DATA, DENALI_CTL_68_DATA,
+	DENALI_CTL_69_DATA,
+	DENALI_CTL_70_DATA, DENALI_CTL_71_DATA, DENALI_CTL_72_DATA,
+	DENALI_CTL_73_DATA, DENALI_CTL_74_DATA, DENALI_CTL_75_DATA,
+	DENALI_CTL_76_DATA, DENALI_CTL_77_DATA, DENALI_CTL_78_DATA,
+	DENALI_CTL_79_DATA,
+	DENALI_CTL_80_DATA, DENALI_CTL_81_DATA, DENALI_CTL_82_DATA,
+	DENALI_CTL_83_DATA, DENALI_CTL_84_DATA, DENALI_CTL_85_DATA,
+	DENALI_CTL_86_DATA, DENALI_CTL_87_DATA, DENALI_CTL_88_DATA,
+	DENALI_CTL_89_DATA,
+	DENALI_CTL_90_DATA, DENALI_CTL_91_DATA, DENALI_CTL_92_DATA,
+	DENALI_CTL_93_DATA, DENALI_CTL_94_DATA, DENALI_CTL_95_DATA,
+	DENALI_CTL_96_DATA, DENALI_CTL_97_DATA, DENALI_CTL_98_DATA,
+	DENALI_CTL_99_DATA,
+
+	DENALI_CTL_100_DATA, DENALI_CTL_101_DATA, DENALI_CTL_102_DATA,
+	DENALI_CTL_103_DATA, DENALI_CTL_104_DATA, DENALI_CTL_105_DATA,
+	DENALI_CTL_106_DATA, DENALI_CTL_107_DATA, DENALI_CTL_108_DATA,
+	DENALI_CTL_109_DATA,
+	DENALI_CTL_110_DATA, DENALI_CTL_111_DATA, DENALI_CTL_112_DATA,
+	DENALI_CTL_113_DATA, DENALI_CTL_114_DATA, DENALI_CTL_115_DATA,
+	DENALI_CTL_116_DATA, DENALI_CTL_117_DATA, DENALI_CTL_118_DATA,
+	DENALI_CTL_119_DATA,
+	DENALI_CTL_120_DATA, DENALI_CTL_121_DATA, DENALI_CTL_122_DATA,
+	DENALI_CTL_123_DATA, DENALI_CTL_124_DATA, DENALI_CTL_125_DATA,
+	DENALI_CTL_126_DATA, DENALI_CTL_127_DATA, DENALI_CTL_128_DATA,
+	DENALI_CTL_129_DATA,
+	DENALI_CTL_130_DATA, DENALI_CTL_131_DATA, DENALI_CTL_132_DATA,
+	DENALI_CTL_133_DATA, DENALI_CTL_134_DATA, DENALI_CTL_135_DATA,
+	DENALI_CTL_136_DATA, DENALI_CTL_137_DATA, DENALI_CTL_138_DATA,
+	DENALI_CTL_139_DATA,
+	DENALI_CTL_140_DATA, DENALI_CTL_141_DATA, DENALI_CTL_142_DATA,
+	DENALI_CTL_143_DATA, DENALI_CTL_144_DATA, DENALI_CTL_145_DATA,
+	DENALI_CTL_146_DATA, DENALI_CTL_147_DATA, DENALI_CTL_148_DATA,
+	DENALI_CTL_149_DATA,
+	DENALI_CTL_150_DATA, DENALI_CTL_151_DATA, DENALI_CTL_152_DATA,
+	DENALI_CTL_153_DATA, DENALI_CTL_154_DATA, DENALI_CTL_155_DATA,
+	DENALI_CTL_156_DATA, DENALI_CTL_157_DATA, DENALI_CTL_158_DATA,
+	DENALI_CTL_159_DATA,
+	DENALI_CTL_160_DATA, DENALI_CTL_161_DATA, DENALI_CTL_162_DATA,
+	DENALI_CTL_163_DATA, DENALI_CTL_164_DATA, DENALI_CTL_165_DATA,
+	DENALI_CTL_166_DATA, DENALI_CTL_167_DATA, DENALI_CTL_168_DATA,
+	DENALI_CTL_169_DATA,
+	DENALI_CTL_170_DATA, DENALI_CTL_171_DATA, DENALI_CTL_172_DATA,
+	DENALI_CTL_173_DATA, DENALI_CTL_174_DATA, DENALI_CTL_175_DATA,
+	DENALI_CTL_176_DATA, DENALI_CTL_177_DATA, DENALI_CTL_178_DATA,
+	DENALI_CTL_179_DATA,
+	DENALI_CTL_180_DATA, DENALI_CTL_181_DATA, DENALI_CTL_182_DATA,
+	DENALI_CTL_183_DATA, DENALI_CTL_184_DATA, DENALI_CTL_185_DATA,
+	DENALI_CTL_186_DATA, DENALI_CTL_187_DATA, DENALI_CTL_188_DATA,
+	DENALI_CTL_189_DATA,
+	DENALI_CTL_190_DATA, DENALI_CTL_191_DATA, DENALI_CTL_192_DATA,
+	DENALI_CTL_193_DATA, DENALI_CTL_194_DATA, DENALI_CTL_195_DATA,
+	DENALI_CTL_196_DATA, DENALI_CTL_197_DATA, DENALI_CTL_198_DATA,
+	DENALI_CTL_199_DATA,
+
+	DENALI_CTL_200_DATA, DENALI_CTL_201_DATA, DENALI_CTL_202_DATA,
+	DENALI_CTL_203_DATA, DENALI_CTL_204_DATA, DENALI_CTL_205_DATA,
+	DENALI_CTL_206_DATA, DENALI_CTL_207_DATA, DENALI_CTL_208_DATA,
+	DENALI_CTL_209_DATA,
+	DENALI_CTL_210_DATA, DENALI_CTL_211_DATA, DENALI_CTL_212_DATA,
+	DENALI_CTL_213_DATA, DENALI_CTL_214_DATA, DENALI_CTL_215_DATA,
+	DENALI_CTL_216_DATA, DENALI_CTL_217_DATA, DENALI_CTL_218_DATA,
+	DENALI_CTL_219_DATA,
+	DENALI_CTL_220_DATA, DENALI_CTL_221_DATA, DENALI_CTL_222_DATA,
+	DENALI_CTL_223_DATA, DENALI_CTL_224_DATA, DENALI_CTL_225_DATA,
+	DENALI_CTL_226_DATA, DENALI_CTL_227_DATA, DENALI_CTL_228_DATA,
+	DENALI_CTL_229_DATA,
+	DENALI_CTL_230_DATA, DENALI_CTL_231_DATA, DENALI_CTL_232_DATA,
+	DENALI_CTL_233_DATA, DENALI_CTL_234_DATA, DENALI_CTL_235_DATA,
+	DENALI_CTL_236_DATA, DENALI_CTL_237_DATA, DENALI_CTL_238_DATA,
+	DENALI_CTL_239_DATA,
+	DENALI_CTL_240_DATA, DENALI_CTL_241_DATA, DENALI_CTL_242_DATA,
+	DENALI_CTL_243_DATA, DENALI_CTL_244_DATA, DENALI_CTL_245_DATA,
+	DENALI_CTL_246_DATA, DENALI_CTL_247_DATA, DENALI_CTL_248_DATA,
+	DENALI_CTL_249_DATA,
+	DENALI_CTL_250_DATA, DENALI_CTL_251_DATA, DENALI_CTL_252_DATA,
+	DENALI_CTL_253_DATA, DENALI_CTL_254_DATA, DENALI_CTL_255_DATA,
+	DENALI_CTL_256_DATA, DENALI_CTL_257_DATA, DENALI_CTL_258_DATA,
+	DENALI_CTL_259_DATA,
+	DENALI_CTL_260_DATA, DENALI_CTL_261_DATA, DENALI_CTL_262_DATA,
+	DENALI_CTL_263_DATA, DENALI_CTL_264_DATA
+};
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 3a5e74f1fb..7cd81e46cc 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -11,6 +11,8 @@ 
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <misc.h>
+#include <spl.h>
+#include "fu540-memory-map.h"
 
 /*
  * This define is a value used for error/unknown serial.
@@ -110,7 +112,30 @@  int misc_init_r(void)
 
 int board_init(void)
 {
-	/* For now nothing to do here. */
+	/* enable all cache ways */
+	ccache_enable_ways(CCACHE_CTRL_ADDR, 15);
+	return 0;
+}
+
+#ifdef CONFIG_SPL
+void board_boot_order(u32 *spl_boot_list)
+{
+	u8 i;
+	u32 boot_devices[] = {
+#ifdef CONFIG_SPL_MMC_SUPPORT
+		BOOT_DEVICE_MMC1,
+#endif
+	};
 
+	for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
+		spl_boot_list[i] = boot_devices[i];
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* boot using first FIT config */
 	return 0;
 }
+#endif
diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c
new file mode 100644
index 0000000000..beeadcae82
--- /dev/null
+++ b/board/sifive/fu540/spl.c
@@ -0,0 +1,307 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel at sifive.com>
+ *   Troy Benjegerdes <troy.benjegerdes at sifive.com>
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <misc.h>
+
+#include "ux00ddr.h"
+#include "fu540-memory-map.h"
+
+#define DDR_SIZE  (8UL * 1024UL * 1024UL * 1024UL)
+#define DDRCTLPLL_F 55
+#define DDRCTLPLL_Q 2
+
+#define PHY_NRESET 0x1000
+#define FIRST_SLOT  0xfe
+#define LAST_SLOT   0x80
+
+static const uintptr_t uart_devices[] = {
+	UART0_CTRL_ADDR,
+	UART1_CTRL_ADDR,
+};
+
+unsigned int serial_to_burn = ~0;
+
+static inline int ux00prci_select_corepll(volatile u32 *coreclkselreg,
+					  volatile u32 *corepllcfg,
+					  volatile u32 *corepllout,
+					  u32 pllconfigval)
+{
+	(*corepllcfg) = pllconfigval;
+
+	// Wait for lock
+	while (((*corepllcfg) & (PLL_LOCK(1))) == 0)
+		;
+
+	u32 core_out =
+		(PLLOUT_DIV(PLLOUT_DIV_default)) |
+		(PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
+		(PLLOUT_CLK_EN(1));
+	(*corepllout) = core_out;
+
+	// Set CORECLKSELREG to select COREPLL
+	(*coreclkselreg) = PLL_CORECLKSEL_COREPLL;
+
+	return 0;
+}
+
+static inline int ux00prci_select_corepll_500mhz(volatile u32 *coreclkselreg,
+						 volatile u32 *corepllcfg,
+						 volatile u32 *corepllout)
+{
+	/*
+	 * CORE pll init
+	 * Set corepll 33MHz -> 1GHz
+	 */
+
+	u32 core500mhz =
+		(PLL_R(0)) |
+		(PLL_F(59)) |            /*4000MHz VCO*/
+		(PLL_Q(3)) |             /* /8 Output divider */
+		(PLL_RANGE(0x4)) |
+		(PLL_BYPASS(0)) |
+		(PLL_FSE(1));
+
+	return ux00prci_select_corepll(coreclkselreg, corepllcfg, corepllout,
+			core500mhz);
+}
+
+static inline int ux00prci_select_corepll_1ghz(volatile u32 *coreclkselreg,
+					       volatile u32 *corepllcfg,
+					       volatile u32 *corepllout)
+{
+	/*
+	 * CORE pll init
+	 * Set corepll 33MHz -> 1GHz
+	 */
+
+	u32 core1ghz =
+		(PLL_R(0)) |
+		(PLL_F(59)) |            /*4000MHz VCO*/
+		(PLL_Q(2)) |             /* /4 Output divider */
+		(PLL_RANGE(0x4)) |
+		(PLL_BYPASS(0)) |
+		(PLL_FSE(1));
+
+	return ux00prci_select_corepll(coreclkselreg, corepllcfg, corepllout,
+			core1ghz);
+}
+
+/*
+ * Get smallest clock divisor that divides input_hz to a quotient less than or
+ * equal to max_target_hz;
+ */
+static inline unsigned int uart_min_clk_divisor(u64 input_hz, u64 max_target_hz)
+{
+	u64 quotient = (input_hz + max_target_hz - 1) / (max_target_hz);
+
+	// Avoid underflow
+	if (quotient == 0)
+		return 0;
+	else
+		return quotient - 1;
+}
+
+/**
+ * Scale uart clock dividers before changing core PLL.
+ */
+void update_uart_clock_dividers(unsigned int peripheral_input_khz)
+{
+	unsigned int uart_target_hz = 115200ULL;
+	unsigned int uart_div = uart_min_clk_divisor(peripheral_input_khz *
+			1000ULL, uart_target_hz);
+
+	for (size_t i = 0; i < ARRAY_SIZE(uart_devices); i++)
+		_REG32(uart_devices[i], UART_REG_DIV) = uart_div;
+}
+
+long nsec_per_cyc = 300; // 33.333MHz
+void nsleep(long nsec)
+{
+	long step = nsec_per_cyc * 2; // 2 instructions per loop iteration
+
+	while (nsec > 0)
+		nsec -= step;
+}
+
+void init_clk_and_ddr(void)
+{
+	// PRCI init
+
+	unsigned long peripheral_input_khz;
+
+	// Check Reset Values (lock don't care)
+	u32 pll_default =
+		(PLL_R(PLL_R_default)) |
+		(PLL_F(PLL_F_default)) |
+		(PLL_Q(PLL_Q_default)) |
+		(PLL_RANGE(PLL_RANGE_default)) |
+		(PLL_BYPASS(PLL_BYPASS_default)) |
+		(PLL_FSE(PLL_FSE_default));
+	u32 lockmask = ~PLL_LOCK(1);
+	u32 pllout_default =
+		(PLLOUT_DIV(PLLOUT_DIV_default)) |
+		(PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
+		(PLLOUT_CLK_EN(PLLOUT_CLK_EN_default));
+
+	if ((UX00PRCI_REG(UX00PRCI_COREPLLCFG)     ^ pll_default) & lockmask)
+		return;
+	if ((UX00PRCI_REG(UX00PRCI_COREPLLOUT)     ^ pllout_default))
+		return;
+	if ((UX00PRCI_REG(UX00PRCI_DDRPLLCFG)      ^ pll_default) & lockmask)
+		return;
+	if ((UX00PRCI_REG(UX00PRCI_DDRPLLOUT)      ^ pllout_default))
+		return;
+	if (((UX00PRCI_REG(UX00PRCI_GEMGXLPLLCFG)) ^ pll_default) & lockmask)
+		return;
+	if (((UX00PRCI_REG(UX00PRCI_GEMGXLPLLOUT)) ^ pllout_default))
+		return;
+
+	//CORE pll init
+	// If tlclksel is set for 2:1 operation,
+	// Set corepll 33Mhz -> 1GHz
+	// Otherwise, set corepll 33MHz -> 500MHz.
+
+	if (UX00PRCI_REG(UX00PRCI_CLKMUXSTATUSREG) & CLKMUX_STATUS_TLCLKSEL) {
+		nsec_per_cyc = 2;
+		peripheral_input_khz = 500000; // peripheral_clk = tlclk
+		update_uart_clock_dividers(peripheral_input_khz);
+		ux00prci_select_corepll_500mhz
+			(&UX00PRCI_REG(UX00PRCI_CORECLKSELREG),
+			 &UX00PRCI_REG(UX00PRCI_COREPLLCFG),
+			 &UX00PRCI_REG(UX00PRCI_COREPLLOUT));
+	} else {
+		nsec_per_cyc = 1;
+		peripheral_input_khz = (1000000 / 2); // peripheral_clk = tlclk
+		update_uart_clock_dividers(peripheral_input_khz);
+
+		ux00prci_select_corepll_1ghz
+			(&UX00PRCI_REG(UX00PRCI_CORECLKSELREG),
+			 &UX00PRCI_REG(UX00PRCI_COREPLLCFG),
+			 &UX00PRCI_REG(UX00PRCI_COREPLLOUT));
+	}
+
+	//
+	//DDR init
+	//
+
+	u32 ddrctlmhz =
+		(PLL_R(0)) |
+		(PLL_F(DDRCTLPLL_F)) |
+		(PLL_Q(DDRCTLPLL_Q)) |
+		(PLL_RANGE(0x4)) |
+		(PLL_BYPASS(0)) |
+		(PLL_FSE(1));
+	UX00PRCI_REG(UX00PRCI_DDRPLLCFG) = ddrctlmhz;
+
+	// Wait for lock
+	while ((UX00PRCI_REG(UX00PRCI_DDRPLLCFG) & PLL_LOCK(1)) == 0)
+		;
+
+	u32 ddrctl_out =
+		(PLLOUT_DIV(PLLOUT_DIV_default)) |
+		(PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
+		(PLLOUT_CLK_EN(1));
+	(UX00PRCI_REG(UX00PRCI_DDRPLLOUT)) = ddrctl_out;
+
+	//Release DDR reset.
+	UX00PRCI_REG(UX00PRCI_DEVICESRESETREG) |=
+		DEVICESRESET_DDR_CTRL_RST_N(1);
+
+	// HACK to get the '1 full controller clock cycle'.
+	asm volatile ("fence");
+	UX00PRCI_REG(UX00PRCI_DEVICESRESETREG) |= DEVICESRESET_DDR_AXI_RST_N(1)
+		| DEVICESRESET_DDR_AHB_RST_N(1) | DEVICESRESET_DDR_PHY_RST_N(1);
+	// HACK to get the '1 full controller clock cycle'.
+	asm volatile ("fence");
+	// These take like 16 cycles to actually propagate. We can't go sending
+	// stuff before they come out of reset. So wait. (TODO: Add a register
+	// to read the current reset states, or DDR Control device?)
+	for (int i = 0; i < 256; i++)
+		asm volatile ("nop");
+
+	ux00ddr_writeregmap(UX00DDR_CTRL_ADDR, ddr_ctl_settings,
+			    ddr_phy_settings);
+	ux00ddr_disableaxireadinterleave(UX00DDR_CTRL_ADDR);
+
+	ux00ddr_disableoptimalrmodw(UX00DDR_CTRL_ADDR);
+
+	ux00ddr_enablewriteleveling(UX00DDR_CTRL_ADDR);
+	ux00ddr_enablereadleveling(UX00DDR_CTRL_ADDR);
+	ux00ddr_enablereadlevelinggate(UX00DDR_CTRL_ADDR);
+	if (ux00ddr_getdramclass(UX00DDR_CTRL_ADDR) == DRAM_CLASS_DDR4)
+		ux00ddr_enablevreftraining(UX00DDR_CTRL_ADDR);
+	//mask off interrupts for leveling completion
+	ux00ddr_mask_leveling_completed_interrupt(UX00DDR_CTRL_ADDR);
+
+	ux00ddr_mask_mc_init_complete_interrupt(UX00DDR_CTRL_ADDR);
+	ux00ddr_mask_outofrange_interrupts(UX00DDR_CTRL_ADDR);
+	ux00ddr_setuprangeprotection(UX00DDR_CTRL_ADDR, DDR_SIZE);
+	ux00ddr_mask_port_command_error_interrupt(UX00DDR_CTRL_ADDR);
+
+	const u64 ddr_size = DDR_SIZE;
+	const u64 ddr_end = CONFIG_SYS_SDRAM_BASE + ddr_size;
+
+	ux00ddr_start(UX00DDR_CTRL_ADDR, PHYSICAL_FILTER_CTRL_ADDR, ddr_end);
+	ux00ddr_phy_fixup(UX00DDR_CTRL_ADDR);
+
+	//
+	//GEMGXL init
+	//
+	u32 gemgxl125mhz =
+		(PLL_R(0)) |
+		(PLL_F(59)) |  /*4000Mhz VCO*/
+		(PLL_Q(5)) |   /* /32 */
+		(PLL_RANGE(0x4)) |
+		(PLL_BYPASS(0)) |
+		(PLL_FSE(1));
+	UX00PRCI_REG(UX00PRCI_GEMGXLPLLCFG) = gemgxl125mhz;
+
+	// Wait for lock
+	while ((UX00PRCI_REG(UX00PRCI_GEMGXLPLLCFG) & PLL_LOCK(1)) == 0)
+		;
+
+	u32 gemgxlctl_out =
+		(PLLOUT_DIV(PLLOUT_DIV_default)) |
+		(PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
+		(PLLOUT_CLK_EN(1));
+	UX00PRCI_REG(UX00PRCI_GEMGXLPLLOUT) = gemgxlctl_out;
+
+	//Release GEMGXL reset (set bit DEVICESRESET_GEMGXL to 1)
+	UX00PRCI_REG(UX00PRCI_DEVICESRESETREG) |= DEVICESRESET_GEMGXL_RST_N(1);
+
+	// VSC8541 PHY reset sequence; leave pull-down active for 2ms
+	nsleep(2000000);
+	// Set GPIO 12 (PHY NRESET) to OE=1 and OVAL=1
+	GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET;
+	GPIO_REG(GPIO_OUTPUT_EN) |= PHY_NRESET;
+	nsleep(100);
+
+	// Procmon => core clock
+	UX00PRCI_REG(UX00PRCI_PROCMONCFG) = 0x1 << 24;
+
+	// Post the serial number and build info
+	UART0_REG(UART_REG_TXCTRL) = UART_TXEN;
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	ret = spl_early_init();
+	if (ret)
+		panic("spl_early_init() failed: %d\n", ret);
+
+	arch_cpu_init_dm();
+
+	init_clk_and_ddr();
+
+	preloader_console_init();
+}
diff --git a/configs/sifive_fu540_spl_defconfig b/configs/sifive_fu540_spl_defconfig
new file mode 100644
index 0000000000..4053743f4c
--- /dev/null
+++ b/configs/sifive_fu540_spl_defconfig
@@ -0,0 +1,26 @@ 
+CONFIG_RISCV=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_SIFIVE_FU540=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_MISC=y
+CONFIG_EMEMORY_OTP=y
+CONFIG_MISC_INIT_R=y
+CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_OF_SEPARATE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_MTD=y
+CONFIG_SPL=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=1
+CONFIG_SPL_CLK=y
+CONFIG_SPL_PAYLOAD="u-boot.itb"
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index 2756ed5a77..ef3ae9b650 100644
--- a/include/configs/sifive-fu540.h
+++ b/include/configs/sifive-fu540.h
@@ -11,6 +11,22 @@ 
 
 #include <linux/sizes.h>
 
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_MAX_SIZE		0x00100000
+#define CONFIG_SPL_BSS_START_ADDR	0x85000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					 CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	0x84000000
+
+#define CONFIG_SPL_STACK	(0x08000000 + 0x001D0000 - \
+				 GENERATED_GBL_DATA_SIZE)
+
+#endif
+
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_2M)
 
@@ -24,6 +40,7 @@ 
 
 /* Environment options */
 
+#ifndef CONFIG_SPL_BUILD
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
 	func(DHCP, dhcp, na)
@@ -43,5 +60,6 @@ 
 #define CONFIG_PREBOOT \
 	"setenv fdt_addr ${fdtcontroladdr};" \
 	"fdt addr ${fdtcontroladdr};"
+#endif
 
 #endif /* __CONFIG_H */