diff mbox series

[v1,1/9] mips: octeon: dts: mrvl, cn73xx.dtsi: Add memory controller DT node

Message ID 20200609094234.248900-2-sr@denx.de
State Accepted
Commit a23c279059723aa7d01a35139f3f3cc941d73f30
Headers show
Series mips: Add Octeon DDR4 init code | expand

Commit Message

Stefan Roese June 9, 2020, 9:42 a.m. UTC 
This patch adds the memory controller (LMC) DT node to the Octeon 3 dtsi
file. It also adds the L2C DT node, as this is referenced by the DDR
driver.

Signed-off-by: Stefan Roese <sr at denx.de>
---

 arch/mips/dts/mrvl,cn73xx.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
diff mbox series

Patch

diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
index 4c7b6e4160..6843a397b2 100644
--- a/arch/mips/dts/mrvl,cn73xx.dtsi
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -64,6 +64,23 @@ 
 				     <0x0300e 4>, <0x0300f 4>;
 		};
 
+		l2c: l2c at 1180080000000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "cavium,octeon-7xxx-l2c";
+			reg = <0x11800 0x80000000 0x0 0x01000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		lmc: lmc at 1180088000000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "cavium,octeon-7xxx-ddr4";
+			reg = <0x11800 0x88000000 0x0 0x02000000>; // 2 IFs
+			u-boot,dm-pre-reloc;
+			l2c-handle = <&l2c>;
+		};
+
 		reset: reset at 1180006001600 {
 			compatible = "mrvl,cn7xxx-rst";
 			reg = <0x11800 0x06001600 0x0 0x200>;