diff mbox series

[v3,02/15] arm: cpu: armv8: add L3 memory flush support

Message ID 20200610104120.30668-3-rayagonda.kokatanur@broadcom.com
State Superseded
Headers show
Series add initial support for broadcom NS3 soc | expand

Commit Message

Rayagonda Kokatanur June 10, 2020, 10:41 a.m. UTC
Add L3 memory flush support for NS3.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com>
---
 arch/arm/cpu/armv8/Makefile          |  1 +
 arch/arm/cpu/armv8/bcmns3/Makefile   |  5 ++
 arch/arm/cpu/armv8/bcmns3/lowlevel.S | 90 ++++++++++++++++++++++++++++
 3 files changed, 96 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/bcmns3/Makefile
 create mode 100644 arch/arm/cpu/armv8/bcmns3/lowlevel.S

Comments

Simon Glass June 17, 2020, 3:11 a.m. UTC | #1
On Wed, 10 Jun 2020 at 04:41, Rayagonda Kokatanur
<rayagonda.kokatanur at broadcom.com> wrote:
>
> Add L3 memory flush support for NS3.
>
> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com>
> ---
>  arch/arm/cpu/armv8/Makefile          |  1 +
>  arch/arm/cpu/armv8/bcmns3/Makefile   |  5 ++
>  arch/arm/cpu/armv8/bcmns3/lowlevel.S | 90 ++++++++++++++++++++++++++++
>  3 files changed, 96 insertions(+)
>  create mode 100644 arch/arm/cpu/armv8/bcmns3/Makefile
>  create mode 100644 arch/arm/cpu/armv8/bcmns3/lowlevel.S
>
> diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
> index 2e48df0eb9..7e33a183d5 100644
> --- a/arch/arm/cpu/armv8/Makefile
> +++ b/arch/arm/cpu/armv8/Makefile
> @@ -39,3 +39,4 @@ obj-$(CONFIG_S32V234) += s32v234/
>  obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
>  obj-$(CONFIG_ARMV8_PSCI) += psci.o
>  obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
> +obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
> diff --git a/arch/arm/cpu/armv8/bcmns3/Makefile b/arch/arm/cpu/armv8/bcmns3/Makefile
> new file mode 100644
> index 0000000000..a35e29d11a
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/bcmns3/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright 2020 Broadcom.
> +
> +obj-y  += lowlevel.o
> diff --git a/arch/arm/cpu/armv8/bcmns3/lowlevel.S b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
> new file mode 100644
> index 0000000000..202286248e
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
> @@ -0,0 +1,90 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2020 Broadcom
> + *
> + * Extracted from fsl-layerscape/lowlevel.S

Should this file be common, then? Is the (c) correct?
Rayagonda Kokatanur June 19, 2020, 4:55 p.m. UTC | #2
Hi Simon,

On Wed, Jun 17, 2020 at 8:42 AM Simon Glass <sjg at chromium.org> wrote:
>
> On Wed, 10 Jun 2020 at 04:41, Rayagonda Kokatanur
> <rayagonda.kokatanur at broadcom.com> wrote:
> >
> > Add L3 memory flush support for NS3.
> >
> > Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com>
> > ---
> >  arch/arm/cpu/armv8/Makefile          |  1 +
> >  arch/arm/cpu/armv8/bcmns3/Makefile   |  5 ++
> >  arch/arm/cpu/armv8/bcmns3/lowlevel.S | 90 ++++++++++++++++++++++++++++
> >  3 files changed, 96 insertions(+)
> >  create mode 100644 arch/arm/cpu/armv8/bcmns3/Makefile
> >  create mode 100644 arch/arm/cpu/armv8/bcmns3/lowlevel.S
> >
> > diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
> > index 2e48df0eb9..7e33a183d5 100644
> > --- a/arch/arm/cpu/armv8/Makefile
> > +++ b/arch/arm/cpu/armv8/Makefile
> > @@ -39,3 +39,4 @@ obj-$(CONFIG_S32V234) += s32v234/
> >  obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
> >  obj-$(CONFIG_ARMV8_PSCI) += psci.o
> >  obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
> > +obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
> > diff --git a/arch/arm/cpu/armv8/bcmns3/Makefile b/arch/arm/cpu/armv8/bcmns3/Makefile
> > new file mode 100644
> > index 0000000000..a35e29d11a
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv8/bcmns3/Makefile
> > @@ -0,0 +1,5 @@
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> > +# Copyright 2020 Broadcom.
> > +
> > +obj-y  += lowlevel.o
> > diff --git a/arch/arm/cpu/armv8/bcmns3/lowlevel.S b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
> > new file mode 100644
> > index 0000000000..202286248e
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
> > @@ -0,0 +1,90 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2020 Broadcom
> > + *
> > + * Extracted from fsl-layerscape/lowlevel.S
>
> Should this file be common, then? Is the (c) correct?

Do you mean, file "arch/arm/cpu/armv8/bcmns3/lowlevel.S" should be
common and for common file copyright tag should be "(C) Copyright
2020"  instead of "Copyright 2020 Broadcom".

Please let me know.

Best regards,
Rayagonda
Simon Glass June 26, 2020, 1:43 a.m. UTC | #3
Hi Rayagonda,

On Fri, 19 Jun 2020 at 10:55, Rayagonda Kokatanur
<rayagonda.kokatanur at broadcom.com> wrote:
>
> Hi Simon,
>
> On Wed, Jun 17, 2020 at 8:42 AM Simon Glass <sjg at chromium.org> wrote:
> >
> > On Wed, 10 Jun 2020 at 04:41, Rayagonda Kokatanur
> > <rayagonda.kokatanur at broadcom.com> wrote:
> > >
> > > Add L3 memory flush support for NS3.
> > >
> > > Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com>
> > > ---
> > >  arch/arm/cpu/armv8/Makefile          |  1 +
> > >  arch/arm/cpu/armv8/bcmns3/Makefile   |  5 ++
> > >  arch/arm/cpu/armv8/bcmns3/lowlevel.S | 90 ++++++++++++++++++++++++++++
> > >  3 files changed, 96 insertions(+)
> > >  create mode 100644 arch/arm/cpu/armv8/bcmns3/Makefile
> > >  create mode 100644 arch/arm/cpu/armv8/bcmns3/lowlevel.S
> > >
> > > diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
> > > index 2e48df0eb9..7e33a183d5 100644
> > > --- a/arch/arm/cpu/armv8/Makefile
> > > +++ b/arch/arm/cpu/armv8/Makefile
> > > @@ -39,3 +39,4 @@ obj-$(CONFIG_S32V234) += s32v234/
> > >  obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
> > >  obj-$(CONFIG_ARMV8_PSCI) += psci.o
> > >  obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
> > > +obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
> > > diff --git a/arch/arm/cpu/armv8/bcmns3/Makefile b/arch/arm/cpu/armv8/bcmns3/Makefile
> > > new file mode 100644
> > > index 0000000000..a35e29d11a
> > > --- /dev/null
> > > +++ b/arch/arm/cpu/armv8/bcmns3/Makefile
> > > @@ -0,0 +1,5 @@
> > > +# SPDX-License-Identifier: GPL-2.0+
> > > +#
> > > +# Copyright 2020 Broadcom.
> > > +
> > > +obj-y  += lowlevel.o
> > > diff --git a/arch/arm/cpu/armv8/bcmns3/lowlevel.S b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
> > > new file mode 100644
> > > index 0000000000..202286248e
> > > --- /dev/null
> > > +++ b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
> > > @@ -0,0 +1,90 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > +/*
> > > + * Copyright 2020 Broadcom
> > > + *
> > > + * Extracted from fsl-layerscape/lowlevel.S
> >
> > Should this file be common, then? Is the (c) correct?
>
> Do you mean, file "arch/arm/cpu/armv8/bcmns3/lowlevel.S" should be
> common and for common file copyright tag should be "(C) Copyright
> 2020"  instead of "Copyright 2020 Broadcom".
>

The comment suggests it was copied from another file, in which case
you should keep the (c) from that file, perhaps adding your own.

But if the two files are the same, can you just have one file and move
it to a common location?

> Please let me know.

Consider yourself let.

Regards,
Simon
Rayagonda Kokatanur June 26, 2020, 9:06 a.m. UTC | #4
Hi Simon,

On Fri, Jun 26, 2020 at 7:13 AM Simon Glass <sjg at chromium.org> wrote:
>
> Hi Rayagonda,
>
> On Fri, 19 Jun 2020 at 10:55, Rayagonda Kokatanur
> <rayagonda.kokatanur at broadcom.com> wrote:
> >
> > Hi Simon,
> >
> > On Wed, Jun 17, 2020 at 8:42 AM Simon Glass <sjg at chromium.org> wrote:
> > >
> > > On Wed, 10 Jun 2020 at 04:41, Rayagonda Kokatanur
> > > <rayagonda.kokatanur at broadcom.com> wrote:
> > > >
> > > > Add L3 memory flush support for NS3.
> > > >
> > > > Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com>
> > > > ---
> > > >  arch/arm/cpu/armv8/Makefile          |  1 +
> > > >  arch/arm/cpu/armv8/bcmns3/Makefile   |  5 ++
> > > >  arch/arm/cpu/armv8/bcmns3/lowlevel.S | 90 ++++++++++++++++++++++++++++
> > > >  3 files changed, 96 insertions(+)
> > > >  create mode 100644 arch/arm/cpu/armv8/bcmns3/Makefile
> > > >  create mode 100644 arch/arm/cpu/armv8/bcmns3/lowlevel.S
> > > >
> > > > diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
> > > > index 2e48df0eb9..7e33a183d5 100644
> > > > --- a/arch/arm/cpu/armv8/Makefile
> > > > +++ b/arch/arm/cpu/armv8/Makefile
> > > > @@ -39,3 +39,4 @@ obj-$(CONFIG_S32V234) += s32v234/
> > > >  obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
> > > >  obj-$(CONFIG_ARMV8_PSCI) += psci.o
> > > >  obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
> > > > +obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
> > > > diff --git a/arch/arm/cpu/armv8/bcmns3/Makefile b/arch/arm/cpu/armv8/bcmns3/Makefile
> > > > new file mode 100644
> > > > index 0000000000..a35e29d11a
> > > > --- /dev/null
> > > > +++ b/arch/arm/cpu/armv8/bcmns3/Makefile
> > > > @@ -0,0 +1,5 @@
> > > > +# SPDX-License-Identifier: GPL-2.0+
> > > > +#
> > > > +# Copyright 2020 Broadcom.
> > > > +
> > > > +obj-y  += lowlevel.o
> > > > diff --git a/arch/arm/cpu/armv8/bcmns3/lowlevel.S b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
> > > > new file mode 100644
> > > > index 0000000000..202286248e
> > > > --- /dev/null
> > > > +++ b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
> > > > @@ -0,0 +1,90 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > > +/*
> > > > + * Copyright 2020 Broadcom
> > > > + *
> > > > + * Extracted from fsl-layerscape/lowlevel.S
> > >
> > > Should this file be common, then? Is the (c) correct?
> >
> > Do you mean, file "arch/arm/cpu/armv8/bcmns3/lowlevel.S" should be
> > common and for common file copyright tag should be "(C) Copyright
> > 2020"  instead of "Copyright 2020 Broadcom".
> >
>
> The comment suggests it was copied from another file, in which case
> you should keep the (c) from that file, perhaps adding your own.
>
> But if the two files are the same, can you just have one file and move
> it to a common location?

The comment is misleading.
Though it is copied from another file but both files are not same.
Let me remove that comment.

Thank you,
Rayagonda

>
> > Please let me know.
>
> Consider yourself let.
>
> Regards,
> Simon
diff mbox series

Patch

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 2e48df0eb9..7e33a183d5 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -39,3 +39,4 @@  obj-$(CONFIG_S32V234) += s32v234/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
 obj-$(CONFIG_ARMV8_PSCI) += psci.o
 obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
+obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
diff --git a/arch/arm/cpu/armv8/bcmns3/Makefile b/arch/arm/cpu/armv8/bcmns3/Makefile
new file mode 100644
index 0000000000..a35e29d11a
--- /dev/null
+++ b/arch/arm/cpu/armv8/bcmns3/Makefile
@@ -0,0 +1,5 @@ 
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 Broadcom.
+
+obj-y	+= lowlevel.o
diff --git a/arch/arm/cpu/armv8/bcmns3/lowlevel.S b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
new file mode 100644
index 0000000000..202286248e
--- /dev/null
+++ b/arch/arm/cpu/armv8/bcmns3/lowlevel.S
@@ -0,0 +1,90 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom
+ *
+ * Extracted from fsl-layerscape/lowlevel.S
+ */
+
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+hnf_pstate_poll:
+	/* x0 has the desired status, return 0 for success, 1 for timeout
+	 * clobber x1, x2, x3, x4, x6, x7
+	 */
+	mov	x1, x0
+	mov	x7, #0			/* flag for timeout */
+	mrs	x3, cntpct_el0		/* read timer */
+	mov	w0, #600
+	mov	w6, #1000
+	mul	w0, w0, w6
+	add	x3, x3, x0		/* timeout after 100 microseconds */
+	mov	x0, #0x18
+	movk	x0, #0x6120, lsl #16	/* HNF0_PSTATE_STATUS */
+	mov	w6, #4			/* HN-F node count */
+1:
+	ldr	x2, [x0]
+	cmp	x2, x1			/* check status */
+	b.eq	2f
+	mrs	x4, cntpct_el0
+	cmp	x4, x3
+	b.ls	1b
+	mov	x7, #1			/* timeout */
+	b	3f
+2:
+	add	x0, x0, #0x10000	/* move to next node */
+	subs	w6, w6, #1
+	cbnz	w6, 1b
+3:
+	mov	x0, x7
+	ret
+
+hnf_set_pstate:
+	/* x0 has the desired state, clobber x1, x2, x6 */
+	mov	x1, x0
+	/* power state to SFONLY */
+	mov	w6, #4			/* HN-F node count */
+	mov	x0, #0x10
+	movk x0, #0x6120, lsl #16		/* HNF0_PSTATE_REQ */
+1:	/* set pstate to sfonly */
+	ldr	x2, [x0]
+	and	x2, x2, #0xfffffffffffffffc	/* & HNFPSTAT_MASK */
+	orr	x2, x2, x1
+	str	x2, [x0]
+	add	x0, x0, #0x10000	/* move to next node */
+	subs	w6, w6, #1
+	cbnz	w6, 1b
+
+	ret
+
+ENTRY(__asm_flush_l3_dcache)
+	/*
+	 * Return status in x0
+	 *    success 0
+	 *    timeout 1 for setting SFONLY, 2 for FAM, 3 for both
+	 */
+	mov	x29, lr
+	mov	x8, #0
+
+	dsb	sy
+	mov	x0, #0x1		/* HNFPSTAT_SFONLY */
+	bl	hnf_set_pstate
+
+	mov	x0, #0x4		/* SFONLY status */
+	bl	hnf_pstate_poll
+	cbz	x0, 1f
+	mov	x8, #1			/* timeout */
+1:
+	dsb	sy
+	mov	x0, #0x3		/* HNFPSTAT_FAM */
+	bl	hnf_set_pstate
+
+	mov	x0, #0xc		/* FAM status */
+	bl	hnf_pstate_poll
+	cbz	x0, 1f
+	add	x8, x8, #0x2
+1:
+	mov	x0, x8
+	mov	lr, x29
+	ret
+ENDPROC(__asm_flush_l3_dcache)