diff mbox series

[V2,3/5] clk: renesas: Add R8A774A1 clock tables

Message ID 20200619135830.501470-4-aford173@gmail.com
State New
Headers show
Series Add Basic support for R8A774A1 (RZ/G2M) | expand

Commit Message

Adam Ford June 19, 2020, 1:58 p.m. UTC 
This sync's the clock tables with the official release from
Renesas' repo based on U-Boot 2018.09 and modified to build into
the latest version of U-Boot.

Signed-off-by: Adam Ford <aford173 at gmail.com>
---
V2:  No Change

Comments

Marek Vasut June 19, 2020, 2:07 p.m. UTC | #1 
On 6/19/20 3:58 PM, Adam Ford wrote:
> This sync's the clock tables with the official release from
> Renesas' repo based on U-Boot 2018.09 and modified to build into
> the latest version of U-Boot.

Can you import the clock table from Linux too ?

[...]

> +static const struct mstp_stop_table r8a774a1_mstp_table[] = {
> +	{ 0x00200000, 0x0, 0x00200000, 0 },
> +	{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
> +	{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
> +	{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
> +	{ 0x80000184, 0x180, 0x80000184, 0 },
> +	{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
> +	{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
> +	{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
> +	{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
> +	{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
> +	{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
> +	{ 0x000000B7, 0x0, 0x000000B7, 0 },
> +};

Can you check whether all those bits are really defined in the MSTP
registers of the SoC ?
Adam Ford June 19, 2020, 3:52 p.m. UTC | #2 
On Fri, Jun 19, 2020 at 9:18 AM Marek Vasut <marek.vasut at gmail.com> wrote:
>
> On 6/19/20 3:58 PM, Adam Ford wrote:
> > This sync's the clock tables with the official release from
> > Renesas' repo based on U-Boot 2018.09 and modified to build into
> > the latest version of U-Boot.
>
> Can you import the clock table from Linux too ?

Sure thing. Doing so actually removed a note for missing clocks.  :-)

>
> [...]
>
> > +static const struct mstp_stop_table r8a774a1_mstp_table[] = {
> > +     { 0x00200000, 0x0, 0x00200000, 0 },
> > +     { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
> > +     { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
> > +     { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
> > +     { 0x80000184, 0x180, 0x80000184, 0 },
> > +     { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
> > +     { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
> > +     { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
> > +     { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
> > +     { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
> > +     { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
> > +     { 0x000000B7, 0x0, 0x000000B7, 0 },
> > +};
>
> Can you check whether all those bits are really defined in the MSTP
> registers of the SoC ?

Can you give me a point on how to interpret this table?  I copied it
from the Renesas release, and it looks the same as the table for the
R8A7796, but I don't know what it's supposed to do.

I found the RZG2M ref manual 1.00, and lists MSTPSR1-10 and
RMSTPCR1-10.  Their initial values vary between revisions of the
silicon for the RZ/G2M, but there are 12 entries in the table, so I am
not even sure I'm looking at the right stuff in the ref manual.


thanks,

adam
Marek Vasut June 19, 2020, 4:03 p.m. UTC | #3 
On 6/19/20 5:52 PM, Adam Ford wrote:
> On Fri, Jun 19, 2020 at 9:18 AM Marek Vasut wrote:
>>
>> On 6/19/20 3:58 PM, Adam Ford wrote:
>>> This sync's the clock tables with the official release from
>>> Renesas' repo based on U-Boot 2018.09 and modified to build into
>>> the latest version of U-Boot.
>>
>> Can you import the clock table from Linux too ?
> 
> Sure thing. Doing so actually removed a note for missing clocks.  :-)

Nice

>> [...]
>>
>>> +static const struct mstp_stop_table r8a774a1_mstp_table[] = {
>>> +     { 0x00200000, 0x0, 0x00200000, 0 },
>>> +     { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
>>> +     { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
>>> +     { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
>>> +     { 0x80000184, 0x180, 0x80000184, 0 },
>>> +     { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
>>> +     { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
>>> +     { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
>>> +     { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
>>> +     { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
>>> +     { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
>>> +     { 0x000000B7, 0x0, 0x000000B7, 0 },
>>> +};
>>
>> Can you check whether all those bits are really defined in the MSTP
>> registers of the SoC ?
> 
> Can you give me a point on how to interpret this table?  I copied it
> from the Renesas release, and it looks the same as the table for the
> R8A7796, but I don't know what it's supposed to do.

Look into renesas_clk_remove() in
drivers/clk/renesas/renesas-cpg-mssr.c

> I found the RZG2M ref manual 1.00, and lists MSTPSR1-10 and
> RMSTPCR1-10.  Their initial values vary between revisions of the
> silicon for the RZ/G2M, but there are 12 entries in the table, so I am
> not even sure I'm looking at the right stuff in the ref manual.

You're looking at the correct part of the manual. The goal is to turn
off all the clock expect required ones before booting Linux. The code
(see above) should make it clear what each line means and which register
is written.
Adam Ford June 21, 2020, 1:37 p.m. UTC | #4 
On Fri, Jun 19, 2020 at 2:08 PM Marek Vasut <marek.vasut at gmail.com> wrote:
>
> On 6/19/20 5:52 PM, Adam Ford wrote:
> > On Fri, Jun 19, 2020 at 9:18 AM Marek Vasut wrote:
> >>
> >> On 6/19/20 3:58 PM, Adam Ford wrote:
> >>> This sync's the clock tables with the official release from
> >>> Renesas' repo based on U-Boot 2018.09 and modified to build into
> >>> the latest version of U-Boot.
> >>
> >> Can you import the clock table from Linux too ?
> >
> > Sure thing. Doing so actually removed a note for missing clocks.  :-)
>
> Nice
>
> >> [...]
> >>
> >>> +static const struct mstp_stop_table r8a774a1_mstp_table[] = {
> >>> +     { 0x00200000, 0x0, 0x00200000, 0 },
> >>> +     { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
> >>> +     { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
> >>> +     { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
> >>> +     { 0x80000184, 0x180, 0x80000184, 0 },
> >>> +     { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
> >>> +     { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
> >>> +     { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
> >>> +     { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
> >>> +     { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
> >>> +     { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
> >>> +     { 0x000000B7, 0x0, 0x000000B7, 0 },
> >>> +};
> >>
> >> Can you check whether all those bits are really defined in the MSTP
> >> registers of the SoC ?
> >
> > Can you give me a point on how to interpret this table?  I copied it
> > from the Renesas release, and it looks the same as the table for the
> > R8A7796, but I don't know what it's supposed to do.
>
> Look into renesas_clk_remove() in
> drivers/clk/renesas/renesas-cpg-mssr.c
>
> > I found the RZG2M ref manual 1.00, and lists MSTPSR1-10 and
> > RMSTPCR1-10.  Their initial values vary between revisions of the
> > silicon for the RZ/G2M, but there are 12 entries in the table, so I am
> > not even sure I'm looking at the right stuff in the ref manual.
>
> You're looking at the correct part of the manual. The goal is to turn
> off all the clock expect required ones before booting Linux. The code
> (see above) should make it clear what each line means and which register
> is written.

This appears to work with a quick test, but I haven't exercised everything yet.

static const struct mstp_stop_table r8a774a1_mstp_table[] = {
{ 0x00000000, 0, 0x00000000, 0 },
{ 0xc3e81000, 0, 0xc3e81000, 0 },
{ 0x000E0FDC, 0, 0x000E0FDC, 0 },
{ 0xD00C7C1F, 0, 0xD00C7C1F, 0 },
{ 0x80000004, 0, 0x80000004, 0 },
{ 0x00DF0006, 0, 0x00DF0006, 0 },
{ 0XC5EACCCE, 0, 0XC5EACCCE, 0 },
{ 0x29E1401C, 0, 0x29E1401C, 0 },
{ 0x00009FF1, 0, 0x00009FF1, 0 },
{ 0xFC4FDFE0, 0, 0xFC4FDFE0, 0 },
{ 0xFFFEFFE8, 0, 0xFFFEFFE8, 0 },
};

I read through registers 1-10, but there doesn't appear to be a
register 0, so I left it as all 0's.
The rest of these I only set the bits based on flags that were
available for the RZ/G2M regardless of their default clock status.

Does this look right to you?  If you think it looks good, I'll submit
another revision.

thanks

adam
Marek Vasut June 21, 2020, 1:59 p.m. UTC | #5 
On 6/21/20 3:37 PM, Adam Ford wrote:
[...]
> static const struct mstp_stop_table r8a774a1_mstp_table[] = {
> { 0x00000000, 0, 0x00000000, 0 },
> { 0xc3e81000, 0, 0xc3e81000, 0 },
> { 0x000E0FDC, 0, 0x000E0FDC, 0 },
> { 0xD00C7C1F, 0, 0xD00C7C1F, 0 },
> { 0x80000004, 0, 0x80000004, 0 },
> { 0x00DF0006, 0, 0x00DF0006, 0 },
> { 0XC5EACCCE, 0, 0XC5EACCCE, 0 },
> { 0x29E1401C, 0, 0x29E1401C, 0 },
> { 0x00009FF1, 0, 0x00009FF1, 0 },
> { 0xFC4FDFE0, 0, 0xFC4FDFE0, 0 },
> { 0xFFFEFFE8, 0, 0xFFFEFFE8, 0 },
> };
> 
> I read through registers 1-10, but there doesn't appear to be a
> register 0, so I left it as all 0's.
> The rest of these I only set the bits based on flags that were
> available for the RZ/G2M regardless of their default clock status.
> 
> Does this look right to you?  If you think it looks good, I'll submit
> another revision.

If it matches the datasheet, then it's fine, thanks.
diff mbox series

Patch

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index e78817829b..284e2138b3 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -48,6 +48,13 @@  config CLK_RCAR_GEN3
 	help
 	  Enable this to support the clocks on Renesas RCar Gen3 SoC.
 
+config CLK_R8A774A1
+        bool "Renesas R8A774A1 clock driver"
+        def_bool y if R8A774A1
+        depends on CLK_RCAR_GEN3
+        help
+          Enable this to support the clocks on Renesas R8A774A1 SoC.
+
 config CLK_R8A7795
 	bool "Renesas R8A7795 clock driver"
 	depends on CLK_RCAR_GEN3
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 88339e9d7e..dd599b757e 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -1,5 +1,6 @@ 
 obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o
 obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
+obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
new file mode 100644
index 0000000000..0341d8e61c
--- /dev/null
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -0,0 +1,343 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas R8A774A1 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2019 Marek Vasut <marek.vasut at gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+	/* Core Clock Outputs exported to DT */
+	LAST_DT_CORE_CLK = R8A774A1_CLK_OSC,
+
+	/* External Input Clocks */
+	CLK_EXTAL,
+	CLK_EXTALR,
+
+	/* Internal Core Clocks */
+	CLK_MAIN,
+	CLK_PLL0,
+	CLK_PLL1,
+	CLK_PLL2,
+	CLK_PLL3,
+	CLK_PLL4,
+	CLK_PLL1_DIV2,
+	CLK_PLL1_DIV4,
+	CLK_S0,
+	CLK_S1,
+	CLK_S2,
+	CLK_S3,
+	CLK_SDSRC,
+	CLK_RPCSRC,
+	CLK_SSPSRC,
+	CLK_RINT,
+
+	/* Module Clocks */
+	MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a774a1_core_clks[] = {
+	/* External Clock Inputs */
+	DEF_INPUT("extal",      CLK_EXTAL),
+	DEF_INPUT("extalr",     CLK_EXTALR),
+
+	/* Internal Core Clocks */
+	DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+	DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+	DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+	DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
+	DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+	DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
+
+	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
+	DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
+	DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
+	DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
+	DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
+	DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
+	DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
+	DEF_FIXED(".rpcsrc",    CLK_RPCSRC,        CLK_PLL1,       2, 1),
+
+	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
+
+	/* Core Clock Outputs */
+	DEF_FIXED("ztr",        R8A774A1_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
+	DEF_FIXED("ztrd2",      R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+	DEF_FIXED("zt",         R8A774A1_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
+	DEF_FIXED("zx",         R8A774A1_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
+	DEF_FIXED("s0d1",       R8A774A1_CLK_S0D1,  CLK_S0,         1, 1),
+	DEF_FIXED("s0d2",       R8A774A1_CLK_S0D2,  CLK_S0,         2, 1),
+	DEF_FIXED("s0d3",       R8A774A1_CLK_S0D3,  CLK_S0,         3, 1),
+	DEF_FIXED("s0d4",       R8A774A1_CLK_S0D4,  CLK_S0,         4, 1),
+	DEF_FIXED("s0d6",       R8A774A1_CLK_S0D6,  CLK_S0,         6, 1),
+	DEF_FIXED("s0d8",       R8A774A1_CLK_S0D8,  CLK_S0,         8, 1),
+	DEF_FIXED("s0d12",      R8A774A1_CLK_S0D12, CLK_S0,        12, 1),
+	DEF_FIXED("s1d1",       R8A774A1_CLK_S1D1,  CLK_S1,         1, 1),
+	DEF_FIXED("s1d2",       R8A774A1_CLK_S1D2,  CLK_S1,         2, 1),
+	DEF_FIXED("s1d4",       R8A774A1_CLK_S1D4,  CLK_S1,         4, 1),
+	DEF_FIXED("s2d1",       R8A774A1_CLK_S2D1,  CLK_S2,         1, 1),
+	DEF_FIXED("s2d2",       R8A774A1_CLK_S2D2,  CLK_S2,         2, 1),
+	DEF_FIXED("s2d4",       R8A774A1_CLK_S2D4,  CLK_S2,         4, 1),
+	DEF_FIXED("s3d1",       R8A774A1_CLK_S3D1,  CLK_S3,         1, 1),
+	DEF_FIXED("s3d2",       R8A774A1_CLK_S3D2,  CLK_S3,         2, 1),
+	DEF_FIXED("s3d4",       R8A774A1_CLK_S3D4,  CLK_S3,         4, 1),
+
+	DEF_GEN3_SD("sd0",      R8A774A1_CLK_SD0,   CLK_SDSRC,     0x074),
+	DEF_GEN3_SD("sd1",      R8A774A1_CLK_SD1,   CLK_SDSRC,     0x078),
+	DEF_GEN3_SD("sd2",      R8A774A1_CLK_SD2,   CLK_SDSRC,     0x268),
+	DEF_GEN3_SD("sd3",      R8A774A1_CLK_SD3,   CLK_SDSRC,     0x26c),
+
+	DEF_GEN3_RPC("rpc",     R8A774A1_CLK_RPC,   CLK_RPCSRC,    0x238),
+
+	DEF_FIXED("cl",         R8A774A1_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
+	DEF_FIXED("cp",         R8A774A1_CLK_CP,    CLK_EXTAL,      2, 1),
+
+	/* NOTE: HDMI, CSI, CAN etc. clock are missing */
+
+	DEF_BASE("r",           R8A774A1_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
+};
+
+static const struct mssr_mod_clk r8a774a1_mod_clks[] = {
+	DEF_MOD("scif5",		 202,	R8A774A1_CLK_S3D4),
+	DEF_MOD("scif4",		 203,	R8A774A1_CLK_S3D4),
+	DEF_MOD("scif3",		 204,	R8A774A1_CLK_S3D4),
+	DEF_MOD("scif1",		 206,	R8A774A1_CLK_S3D4),
+	DEF_MOD("scif0",		 207,	R8A774A1_CLK_S3D4),
+	DEF_MOD("msiof3",		 208,	R8A774A1_CLK_MSO),
+	DEF_MOD("msiof2",		 209,	R8A774A1_CLK_MSO),
+	DEF_MOD("msiof1",		 210,	R8A774A1_CLK_MSO),
+	DEF_MOD("msiof0",		 211,	R8A774A1_CLK_MSO),
+	DEF_MOD("sys-dmac2",		 217,	R8A774A1_CLK_S0D3),
+	DEF_MOD("sys-dmac1",		 218,	R8A774A1_CLK_S0D3),
+	DEF_MOD("sys-dmac0",		 219,	R8A774A1_CLK_S0D3),
+	DEF_MOD("cmt3",			 300,	R8A774A1_CLK_R),
+	DEF_MOD("cmt2",			 301,	R8A774A1_CLK_R),
+	DEF_MOD("cmt1",			 302,	R8A774A1_CLK_R),
+	DEF_MOD("cmt0",			 303,	R8A774A1_CLK_R),
+	DEF_MOD("scif2",		 310,	R8A774A1_CLK_S3D4),
+	DEF_MOD("sdif3",		 311,	R8A774A1_CLK_SD3),
+	DEF_MOD("sdif2",		 312,	R8A774A1_CLK_SD2),
+	DEF_MOD("sdif1",		 313,	R8A774A1_CLK_SD1),
+	DEF_MOD("sdif0",		 314,	R8A774A1_CLK_SD0),
+	DEF_MOD("pcie1",		 318,	R8A774A1_CLK_S3D1),
+	DEF_MOD("pcie0",		 319,	R8A774A1_CLK_S3D1),
+	DEF_MOD("usb3-if0",		 328,	R8A774A1_CLK_S3D1),
+	DEF_MOD("usb-dmac0",		 330,	R8A774A1_CLK_S3D1),
+	DEF_MOD("usb-dmac1",		 331,	R8A774A1_CLK_S3D1),
+	DEF_MOD("rwdt",			 402,	R8A774A1_CLK_R),
+	DEF_MOD("intc-ex",		 407,	R8A774A1_CLK_CP),
+	DEF_MOD("intc-ap",		 408,	R8A774A1_CLK_S3D1),
+	DEF_MOD("audmac1",		 501,	R8A774A1_CLK_S0D3),
+	DEF_MOD("audmac0",		 502,	R8A774A1_CLK_S0D3),
+	DEF_MOD("drif31",		 508,	R8A774A1_CLK_S3D2),
+	DEF_MOD("drif30",		 509,	R8A774A1_CLK_S3D2),
+	DEF_MOD("drif21",		 510,	R8A774A1_CLK_S3D2),
+	DEF_MOD("drif20",		 511,	R8A774A1_CLK_S3D2),
+	DEF_MOD("drif11",		 512,	R8A774A1_CLK_S3D2),
+	DEF_MOD("drif10",		 513,	R8A774A1_CLK_S3D2),
+	DEF_MOD("drif01",		 514,	R8A774A1_CLK_S3D2),
+	DEF_MOD("drif00",		 515,	R8A774A1_CLK_S3D2),
+	DEF_MOD("hscif4",		 516,	R8A774A1_CLK_S3D1),
+	DEF_MOD("hscif3",		 517,	R8A774A1_CLK_S3D1),
+	DEF_MOD("hscif2",		 518,	R8A774A1_CLK_S3D1),
+	DEF_MOD("hscif1",		 519,	R8A774A1_CLK_S3D1),
+	DEF_MOD("hscif0",		 520,	R8A774A1_CLK_S3D1),
+	DEF_MOD("thermal",		 522,	R8A774A1_CLK_CP),
+	DEF_MOD("pwm",			 523,	R8A774A1_CLK_S0D12),
+	DEF_MOD("fcpvd2",		 601,	R8A774A1_CLK_S0D2),
+	DEF_MOD("fcpvd1",		 602,	R8A774A1_CLK_S0D2),
+	DEF_MOD("fcpvd0",		 603,	R8A774A1_CLK_S0D2),
+	DEF_MOD("fcpvb0",		 607,	R8A774A1_CLK_S0D1),
+	DEF_MOD("fcpvi0",		 611,	R8A774A1_CLK_S0D1),
+	DEF_MOD("fcpf0",		 615,	R8A774A1_CLK_S0D1),
+	DEF_MOD("fcpci0",		 617,	R8A774A1_CLK_S0D2),
+	DEF_MOD("fcpcs",		 619,	R8A774A1_CLK_S0D2),
+	DEF_MOD("vspd2",		 621,	R8A774A1_CLK_S0D2),
+	DEF_MOD("vspd1",		 622,	R8A774A1_CLK_S0D2),
+	DEF_MOD("vspd0",		 623,	R8A774A1_CLK_S0D2),
+	DEF_MOD("vspb",			 626,	R8A774A1_CLK_S0D1),
+	DEF_MOD("vspi0",		 631,	R8A774A1_CLK_S0D1),
+	DEF_MOD("ehci1",		 702,	R8A774A1_CLK_S3D4),
+	DEF_MOD("ehci0",		 703,	R8A774A1_CLK_S3D4),
+	DEF_MOD("hsusb",		 704,	R8A774A1_CLK_S3D4),
+	DEF_MOD("csi20",		 714,	R8A774A1_CLK_CSI0),
+	DEF_MOD("csi40",		 716,	R8A774A1_CLK_CSI0),
+	DEF_MOD("du2",			 722,	R8A774A1_CLK_S2D1),
+	DEF_MOD("du1",			 723,	R8A774A1_CLK_S2D1),
+	DEF_MOD("du0",			 724,	R8A774A1_CLK_S2D1),
+	DEF_MOD("lvds",			 727,	R8A774A1_CLK_S2D1),
+	DEF_MOD("hdmi0",		 729,	R8A774A1_CLK_HDMI),
+	DEF_MOD("vin7",			 804,	R8A774A1_CLK_S0D2),
+	DEF_MOD("vin6",			 805,	R8A774A1_CLK_S0D2),
+	DEF_MOD("vin5",			 806,	R8A774A1_CLK_S0D2),
+	DEF_MOD("vin4",			 807,	R8A774A1_CLK_S0D2),
+	DEF_MOD("vin3",			 808,	R8A774A1_CLK_S0D2),
+	DEF_MOD("vin2",			 809,	R8A774A1_CLK_S0D2),
+	DEF_MOD("vin1",			 810,	R8A774A1_CLK_S0D2),
+	DEF_MOD("vin0",			 811,	R8A774A1_CLK_S0D2),
+	DEF_MOD("etheravb",		 812,	R8A774A1_CLK_S0D6),
+	DEF_MOD("imr1",			 822,	R8A774A1_CLK_S0D2),
+	DEF_MOD("imr0",			 823,	R8A774A1_CLK_S0D2),
+	DEF_MOD("gpio7",		 905,	R8A774A1_CLK_S3D4),
+	DEF_MOD("gpio6",		 906,	R8A774A1_CLK_S3D4),
+	DEF_MOD("gpio5",		 907,	R8A774A1_CLK_S3D4),
+	DEF_MOD("gpio4",		 908,	R8A774A1_CLK_S3D4),
+	DEF_MOD("gpio3",		 909,	R8A774A1_CLK_S3D4),
+	DEF_MOD("gpio2",		 910,	R8A774A1_CLK_S3D4),
+	DEF_MOD("gpio1",		 911,	R8A774A1_CLK_S3D4),
+	DEF_MOD("gpio0",		 912,	R8A774A1_CLK_S3D4),
+	DEF_MOD("can-fd",		 914,	R8A774A1_CLK_S3D2),
+	DEF_MOD("can-if1",		 915,	R8A774A1_CLK_S3D4),
+	DEF_MOD("can-if0",		 916,	R8A774A1_CLK_S3D4),
+	DEF_MOD("rpc",			 917,	R8A774A1_CLK_RPC),
+	DEF_MOD("i2c6",			 918,	R8A774A1_CLK_S0D6),
+	DEF_MOD("i2c5",			 919,	R8A774A1_CLK_S0D6),
+	DEF_MOD("i2c-dvfs",		 926,	R8A774A1_CLK_CP),
+	DEF_MOD("i2c4",			 927,	R8A774A1_CLK_S0D6),
+	DEF_MOD("i2c3",			 928,	R8A774A1_CLK_S0D6),
+	DEF_MOD("i2c2",			 929,	R8A774A1_CLK_S3D2),
+	DEF_MOD("i2c1",			 930,	R8A774A1_CLK_S3D2),
+	DEF_MOD("i2c0",			 931,	R8A774A1_CLK_S3D2),
+	DEF_MOD("ssi-all",		1005,	R8A774A1_CLK_S3D4),
+	DEF_MOD("ssi9",			1006,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi8",			1007,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi7",			1008,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi6",			1009,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi5",			1010,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi4",			1011,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi3",			1012,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi2",			1013,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi1",			1014,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi0",			1015,	MOD_CLK_ID(1005)),
+	DEF_MOD("scu-all",		1017,	R8A774A1_CLK_S3D4),
+	DEF_MOD("scu-dvc1",		1018,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-dvc0",		1019,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-ctu1-mix1",	1020,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-ctu0-mix0",	1021,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src9",		1022,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src8",		1023,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src7",		1024,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src6",		1025,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src5",		1026,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src4",		1027,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src3",		1028,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src2",		1029,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src1",		1030,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src0",		1031,	MOD_CLK_ID(1017)),
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ *   MD		EXTAL		PLL0	PLL1	PLL2	PLL3	PLL4
+ * 14 13 19 17	(MHz)
+ *-------------------------------------------------------------------
+ * 0  0  0  0	16.66 x 1	x180	x192	x144	x192	x144
+ * 0  0  0  1	16.66 x 1	x180	x192	x144	x128	x144
+ * 0  0  1  0	Prohibited setting
+ * 0  0  1  1	16.66 x 1	x180	x192	x144	x192	x144
+ * 0  1  0  0	20    x 1	x150	x160	x120	x160	x120
+ * 0  1  0  1	20    x 1	x150	x160	x120	x106	x120
+ * 0  1  1  0	Prohibited setting
+ * 0  1  1  1	20    x 1	x150	x160	x120	x160	x120
+ * 1  0  0  0	25    x 1	x120	x128	x96	x128	x96
+ * 1  0  0  1	25    x 1	x120	x128	x96	x84	x96
+ * 1  0  1  0	Prohibited setting
+ * 1  0  1  1	25    x 1	x120	x128	x96	x128	x96
+ * 1  1  0  0	33.33 / 2	x180	x192	x144	x192	x144
+ * 1  1  0  1	33.33 / 2	x180	x192	x144	x128	x144
+ * 1  1  1  0	Prohibited setting
+ * 1  1  1  1	33.33 / 2	x180	x192	x144	x192	x144
+ */
+#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 11) | \
+					 (((md) & BIT(13)) >> 11) | \
+					 (((md) & BIT(19)) >> 18) | \
+					 (((md) & BIT(17)) >> 17))
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+	/* EXTAL div	PLL1 mult/div	PLL3 mult/div   OSC prediv */
+	{ 1,		192,	1,	192,	1,	16,	},
+	{ 1,		192,	1,	128,	1,	16,	},
+	{ 0, /* Prohibited setting */				},
+	{ 1,		192,	1,	192,	1,	16,	},
+	{ 1,		160,	1,	160,	1,	16,	},
+	{ 1,		160,	1,	106,	1,	16,	},
+	{ 0, /* Prohibited setting */				},
+	{ 1,		160,	1,	160,	1,	16,	},
+	{ 1,		128,	1,	128,	1,	16,	},
+	{ 1,		128,	1,	84,	1,	16,	},
+	{ 0, /* Prohibited setting */				},
+	{ 1,		128,	1,	128,	1,	16,	},
+	{ 2,		192,	1,	192,	1,	16,	},
+	{ 2,		192,	1,	128,	1,	16,	},
+	{ 0, /* Prohibited setting */				},
+	{ 2,		192,	1,	192,	1,	16,	},
+};
+
+static const struct mstp_stop_table r8a774a1_mstp_table[] = {
+	{ 0x00200000, 0x0, 0x00200000, 0 },
+	{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+	{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
+	{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
+	{ 0x80000184, 0x180, 0x80000184, 0 },
+	{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
+	{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+	{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+	{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
+	{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
+	{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
+	{ 0x000000B7, 0x0, 0x000000B7, 0 },
+};
+
+static const void *r8a774a1_get_pll_config(const u32 cpg_mode)
+{
+	return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a774a1_cpg_mssr_info = {
+	.core_clk		= r8a774a1_core_clks,
+	.core_clk_size		= ARRAY_SIZE(r8a774a1_core_clks),
+	.mod_clk		= r8a774a1_mod_clks,
+	.mod_clk_size		= ARRAY_SIZE(r8a774a1_mod_clks),
+	.mstp_table		= r8a774a1_mstp_table,
+	.mstp_table_size	= ARRAY_SIZE(r8a774a1_mstp_table),
+	.reset_node		= "renesas,r8a774a1-rst",
+	.extalr_node		= "extalr",
+	.mod_clk_base		= MOD_CLK_BASE,
+	.clk_extal_id		= CLK_EXTAL,
+	.clk_extalr_id		= CLK_EXTALR,
+	.get_pll_config		= r8a774a1_get_pll_config,
+};
+
+static const struct udevice_id r8a774a1_clk_ids[] = {
+	{
+		.compatible	= "renesas,r8a774a1-cpg-mssr",
+		.data		= (ulong)&r8a774a1_cpg_mssr_info,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(clk_r8a774a1) = {
+	.name		= "clk_r8a774a1",
+	.id		= UCLASS_CLK,
+	.of_match	= r8a774a1_clk_ids,
+	.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+	.ops		= &gen3_clk_ops,
+	.probe		= gen3_clk_probe,
+	.remove		= gen3_clk_remove,
+};