| Message ID | 1592745008-17196-5-git-send-email-sagar.kadam@sifive.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | update clock handler and proper cpu features | expand |
On Sun, Jun 21, 2020 at 9:10 PM Sagar Shrikant Kadam <sagar.kadam at sifive.com> wrote: > > All cpu cores within FU540-C000 having split I/D caches. > Set the L1 cache feature bit using the i-cache-size as one of the > property from device tree indicating that L1 cache is present > on the cpu core. > > => cpu detail > 0: cpu at 0 rv64imac > ID = 0, freq = 999.100 MHz: L1 cache > 1: cpu at 1 rv64imafdc > ID = 1, freq = 999.100 MHz: L1 cache, MMU > 2: cpu at 2 rv64imafdc > ID = 2, freq = 999.100 MHz: L1 cache, MMU > 3: cpu at 3 rv64imafdc > ID = 3, freq = 999.100 MHz: L1 cache, MMU > 4: cpu at 4 rv64imafdc > ID = 4, freq = 999.100 MHz: L1 cache, MMU > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com> > Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com> > --- > drivers/cpu/riscv_cpu.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c > index 8c4b5e7..ce722cb 100644 > --- a/drivers/cpu/riscv_cpu.c > +++ b/drivers/cpu/riscv_cpu.c > @@ -35,6 +35,7 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) > int ret; > struct clk clk; > const char *mmu; > + u32 split_cache_size; > > /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */ > info->cpu_freq = 0; > @@ -57,6 +58,11 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) > if (mmu) > info->features |= BIT(CPU_FEAT_MMU); > > + /* check if I/D cache is present */ > + ret = dev_read_u32(dev, "i-cache-size", &split_cache_size); What about testing either "i-cache-size" and "d-cache-size", and if either one exists, set CPU_FEAT_L1_CACHE > + if (!ret) > + info->features |= BIT(CPU_FEAT_L1_CACHE); > + > return 0; > } Regards, Bin
Hi Bin, > -----Original Message----- > From: Bin Meng <bmeng.cn at gmail.com> > Sent: Wednesday, June 24, 2020 6:58 AM > To: Sagar Kadam <sagar.kadam at sifive.com>; Simon Glass > <sjg at chromium.org> > Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Rick Chen > <rick at andestech.com>; Lukasz Majewski <lukma at denx.de>; Jagan Teki > <jagan at amarulasolutions.com>; Pragnesh Patel > <pragnesh.patel at sifive.com>; Anup Patel <anup.patel at wdc.com>; Sean > Anderson <seanga2 at gmail.com> > Subject: Re: [PATCH v4 4/4] riscv: cpu: check and append L1 cache to cpu > features > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Sun, Jun 21, 2020 at 9:10 PM Sagar Shrikant Kadam > <sagar.kadam at sifive.com> wrote: > > > > All cpu cores within FU540-C000 having split I/D caches. > > Set the L1 cache feature bit using the i-cache-size as one of the > > property from device tree indicating that L1 cache is present > > on the cpu core. > > > > => cpu detail > > 0: cpu at 0 rv64imac > > ID = 0, freq = 999.100 MHz: L1 cache > > 1: cpu at 1 rv64imafdc > > ID = 1, freq = 999.100 MHz: L1 cache, MMU > > 2: cpu at 2 rv64imafdc > > ID = 2, freq = 999.100 MHz: L1 cache, MMU > > 3: cpu at 3 rv64imafdc > > ID = 3, freq = 999.100 MHz: L1 cache, MMU > > 4: cpu at 4 rv64imafdc > > ID = 4, freq = 999.100 MHz: L1 cache, MMU > > > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com> > > Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com> > > --- > > drivers/cpu/riscv_cpu.c | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c > > index 8c4b5e7..ce722cb 100644 > > --- a/drivers/cpu/riscv_cpu.c > > +++ b/drivers/cpu/riscv_cpu.c > > @@ -35,6 +35,7 @@ static int riscv_cpu_get_info(struct udevice *dev, > struct cpu_info *info) > > int ret; > > struct clk clk; > > const char *mmu; > > + u32 split_cache_size; > > > > /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */ > > info->cpu_freq = 0; > > @@ -57,6 +58,11 @@ static int riscv_cpu_get_info(struct udevice *dev, > struct cpu_info *info) > > if (mmu) > > info->features |= BIT(CPU_FEAT_MMU); > > > > + /* check if I/D cache is present */ > > + ret = dev_read_u32(dev, "i-cache-size", &split_cache_size); > > What about testing either "i-cache-size" and "d-cache-size", and if > either one exists, set CPU_FEAT_L1_CACHE > Ok. I will repost it with d-cache check as well. Thanks & BR, Sagar Kadam > > + if (!ret) > > + info->features |= BIT(CPU_FEAT_L1_CACHE); > > + > > return 0; > > } > > Regards, > Bin
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 8c4b5e7..ce722cb 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -35,6 +35,7 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) int ret; struct clk clk; const char *mmu; + u32 split_cache_size; /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */ info->cpu_freq = 0; @@ -57,6 +58,11 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) if (mmu) info->features |= BIT(CPU_FEAT_MMU); + /* check if I/D cache is present */ + ret = dev_read_u32(dev, "i-cache-size", &split_cache_size); + if (!ret) + info->features |= BIT(CPU_FEAT_L1_CACHE); + return 0; }
All cpu cores within FU540-C000 having split I/D caches. Set the L1 cache feature bit using the i-cache-size as one of the property from device tree indicating that L1 cache is present on the cpu core. => cpu detail 0: cpu at 0 rv64imac ID = 0, freq = 999.100 MHz: L1 cache 1: cpu at 1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU 2: cpu at 2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU 3: cpu at 3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU 4: cpu at 4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com> --- drivers/cpu/riscv_cpu.c | 6 ++++++ 1 file changed, 6 insertions(+)