diff mbox series

board: fsl: lx2160a: fix SDHC1_DAT4 signal routing

Message ID 20200319071854.3045-1-yangbo.lu@nxp.com
State Accepted
Commit 515f32973aa52ba75758b08606b447c82852cd80
Headers show
Series board: fsl: lx2160a: fix SDHC1_DAT4 signal routing | expand

Commit Message

Y.b. Lu March 19, 2020, 7:18 a.m. UTC
The SDHC1_DAT4 signal could be routes to SDHC1_VS or SDHC1
adapter slot for SDHC1 usage. When SDHC1 is selected in RCW,
do not force to route it to SDHC1 adapter slot if find it
has already been configued for SDHC1_VS.

Signed-off-by: Yangbo Lu <yangbo.lu at nxp.com>
---
 board/freescale/lx2160a/lx2160a.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

Comments

Priyanka Jain (OSS) March 30, 2020, 11:33 a.m. UTC | #1
>-----Original Message-----
>From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Yangbo Lu
>Sent: Thursday, March 19, 2020 12:49 PM
>To: u-boot at lists.denx.de; Priyanka Jain <priyanka.jain at nxp.com>
>Cc: Y.b. Lu <yangbo.lu at nxp.com>
>Subject: [PATCH] board: fsl: lx2160a: fix SDHC1_DAT4 signal routing
>
>The SDHC1_DAT4 signal could be routes to SDHC1_VS or SDHC1 adapter slot
>for SDHC1 usage. When SDHC1 is selected in RCW, do not force to route it to
>SDHC1 adapter slot if find it has already been configued for SDHC1_VS.
>
>Signed-off-by: Yangbo Lu <yangbo.lu at nxp.com>
>---
Applied to u-boot-fsl-qoriq. Waiting upstream

Thanks
Priyanka
diff mbox series

Patch

diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 103b0cc..5ee46f4 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -469,10 +469,16 @@  int config_board_mux(void)
 		reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 		QIXIS_WRITE(brdcfg[11], reg11);
 	} else {
-		/*  Routes {SDHC1_DAT4} to SDHC1 adapter slot */
+		/*
+		 * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
+		 * do not change it.
+		 * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
+		 */
 		reg11 = QIXIS_READ(brdcfg[11]);
-		reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
-		QIXIS_WRITE(brdcfg[11], reg11);
+		if ((reg11 & 0x30) != 0x30) {
+			reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
+			QIXIS_WRITE(brdcfg[11], reg11);
+		}
 
 		/* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 		 * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.