| Message ID | 20200323201519.20341-18-p.yadav@ti.com |
|---|---|
| State | New |
| Headers | show |
| Series | mtd: spi-nor-core: add xSPI Octal DTR support | expand |
diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi index 8497ff3e3e..dfd0bea7be 100644 --- a/arch/arm/dts/k3-j721e-som-p0.dtsi +++ b/arch/arm/dts/k3-j721e-som-p0.dtsi @@ -85,14 +85,14 @@ flash at 0{ compatible = "jedec,spi-nor"; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; + spi-max-frequency = <25000000>; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; - cdns,read-delay = <0>; + cdns,read-delay = <4>; #address-cells = <1>; #size-cells = <1>; };
The Cypress Semper flash supports octal DTR mode, so update the device tree settings to use 8 data lines for both Rx and Tx and allow using DTR mode on both lines. The read delay is set to 4. The calibration sequence yields a value of 2 but since the sequence is run before the flash is switched to octal DTR mode, it gets that value for legacy mode. In octal DTR mode the flash needs a read delay of 4. Setting read delay here over-rides the calibrated value. Signed-off-by: Pratyush Yadav <p.yadav at ti.com> --- These are the DT changes I made to test the series. arch/arm/dts/k3-j721e-som-p0.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.25.0