diff mbox series

[v8,19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot

Message ID 20200509143037.26009-20-pragnesh.patel@sifive.com
State New
Headers show
Series RISC-V SiFive FU540 support SPL | expand

Commit Message

Pragnesh Patel May 9, 2020, 2:30 p.m. UTC
Add L2 cache node to enable cache ways from U-Boot

Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
---
 arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Jagan Teki May 10, 2020, 3:14 p.m. UTC | #1
On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel at sifive.com> wrote:
>
> Add L2 cache node to enable cache ways from U-Boot
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> ---
>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> index fc91a7c987..42e43522ed 100644
> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> @@ -82,3 +82,7 @@
>  &qspi2 {
>         u-boot,dm-spl;
>  };
> +
> +&l2cache {
> +       status = "okay";
> +};

Squash with next commit.
Pragnesh Patel May 11, 2020, 6:06 a.m. UTC | #2
>-----Original Message-----
>From: Jagan Teki <jagan at amarulasolutions.com>
>Sent: 10 May 2020 20:44
>To: Pragnesh Patel <pragnesh.patel at sifive.com>
>Cc: U-Boot-Denx <u-boot at lists.denx.de>; Atish Patra
><atish.patra at wdc.com>; Palmer Dabbelt <palmerdabbelt at google.com>; Bin
>Meng <bmeng.cn at gmail.com>; Paul Walmsley <paul.walmsley at sifive.com>;
>Troy Benjegerdes <troy.benjegerdes at sifive.com>; Anup Patel
><anup.patel at wdc.com>; Sagar Kadam <sagar.kadam at sifive.com>; Rick Chen
><rick at andestech.com>
>Subject: Re: [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel at sifive.com>
>wrote:
>>
>> Add L2 cache node to enable cache ways from U-Boot
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
>> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
>> ---
>>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-
>c000-u-boot.dtsi
>> index fc91a7c987..42e43522ed 100644
>> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> @@ -82,3 +82,7 @@
>>  &qspi2 {
>>         u-boot,dm-spl;
>>  };
>> +
>> +&l2cache {
>> +       status = "okay";
>> +};
>
>Squash with next commit.

Will update in v9.
diff mbox series

Patch

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index fc91a7c987..42e43522ed 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -82,3 +82,7 @@ 
 &qspi2 {
 	u-boot,dm-spl;
 };
+
+&l2cache {
+	status = "okay";
+};