| Message ID | 20200514095912.14428-3-sr@denx.de |
|---|---|
| State | New |
| Headers | show |
| Series | mips: Add initial Octeon MIPS64 base support | expand |
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index f601662cd0..b3c9978a83 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -249,10 +249,12 @@ wr_done: nop # endif +# ifndef CONFIG_ARCH_OCTEON /* Initialize caches... */ PTR_LA t9, mips_cache_reset jalr t9 nop +# endif # ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* Initialize any external memory */
Since Octeon now runs from L2 cache, we can't reset the cache at this time. So let's opt-out this function on Octeon, as the cache is coherent on Octeon anyways. Signed-off-by: Stefan Roese <sr at denx.de> --- Changes in v2: - New patch arch/mips/cpu/start.S | 2 ++ 1 file changed, 2 insertions(+)