| Message ID | bd6bd6c9-fe55-1995-10c1-56c77f110897@siemens.com |
|---|---|
| State | Accepted |
| Commit | c02712a7484918648e5dd09c092035c7eeb7794a |
| Headers | show |
| Series | arm: mach-k3: Enable dcache in SPL | expand |
Hi Jan, On 18/05/20 11:27 am, Jan Kiszka wrote: > From: Jan Kiszka <jan.kiszka at siemens.com> > > Add support for enabling dcache already in SPL. It accelerates the boot > and resolves the risk to run into unaligned 64-bit accesses. > > Based on original patch by Lokesh Vulta. > > Signed-off-by: Jan Kiszka <jan.kiszka at siemens.com> Thanks for the patch. I guess both R5 SPL and A53 SPL caches gets enabled with this patch? Thanks and regards, Lokesh > --- > arch/arm/mach-k3/am6_init.c | 1 + > arch/arm/mach-k3/common.c | 35 +++++++++++++++++++++++++++++++++++ > arch/arm/mach-k3/common.h | 1 + > arch/arm/mach-k3/j721e_init.c | 1 + > board/ti/am65x/evm.c | 2 ++ > 5 files changed, 40 insertions(+) > > diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c > index b692806352..586f5c022e 100644 > --- a/arch/arm/mach-k3/am6_init.c > +++ b/arch/arm/mach-k3/am6_init.c > @@ -197,6 +197,7 @@ void board_init_f(ulong dummy) > if (ret) > panic("DRAM init failed: %d\n", ret); > #endif > + spl_enable_dcache(); > } > > u32 spl_mmc_boot_mode(const u32 boot_device) > diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c > index 80dfa5f0fd..a94e054491 100644 > --- a/arch/arm/mach-k3/common.c > +++ b/arch/arm/mach-k3/common.c > @@ -406,3 +406,38 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) > } > } > } > + > +void spl_enable_dcache(void) > +{ > +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) > + phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; > + > + dram_init_banksize(); > + > + /* reserve TLB table */ > + gd->arch.tlb_size = PGTABLE_SIZE; > + > + ram_top += get_effective_memsize(); > + /* keep ram_top in the 32-bit address space */ > + if (ram_top >= 0x100000000) > + ram_top = (phys_addr_t) 0x100000000; > + > + gd->arch.tlb_addr = ram_top - gd->arch.tlb_size; > + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, > + gd->arch.tlb_addr + gd->arch.tlb_size); > + > + dcache_enable(); > +#endif > +} > + > +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) > +void spl_board_prepare_for_boot(void) > +{ > + dcache_disable(); > +} > + > +void spl_board_prepare_for_boot_linux(void) > +{ > + dcache_disable(); > +} > +#endif > diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h > index 57682e1973..94cdcb56ad 100644 > --- a/arch/arm/mach-k3/common.h > +++ b/arch/arm/mach-k3/common.h > @@ -27,3 +27,4 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size); > void start_non_linux_remote_cores(void); > int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr); > void k3_sysfw_print_ver(void); > +void spl_enable_dcache(void); > diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c > index 71fc20c30b..3ffdb6f258 100644 > --- a/arch/arm/mach-k3/j721e_init.c > +++ b/arch/arm/mach-k3/j721e_init.c > @@ -221,6 +221,7 @@ void board_init_f(ulong dummy) > if (ret) > panic("DRAM init failed: %d\n", ret); > #endif > + spl_enable_dcache(); > } > > u32 spl_mmc_boot_mode(const u32 boot_device) > diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c > index a610879424..2da7db9f09 100644 > --- a/board/ti/am65x/evm.c > +++ b/board/ti/am65x/evm.c > @@ -69,11 +69,13 @@ int dram_init_banksize(void) > /* Bank 0 declares the memory available in the DDR low region */ > gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; > gd->bd->bi_dram[0].size = 0x80000000; > + gd->ram_size = 0x80000000; > > #ifdef CONFIG_PHYS_64BIT > /* Bank 1 declares the memory available in the DDR high region */ > gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; > gd->bd->bi_dram[1].size = 0x80000000; > + gd->ram_size = 0x100000000; > #endif > > return 0; >
On 19.05.20 08:18, Lokesh Vutla wrote: > Hi Jan, > > On 18/05/20 11:27 am, Jan Kiszka wrote: >> From: Jan Kiszka <jan.kiszka at siemens.com> >> >> Add support for enabling dcache already in SPL. It accelerates the boot >> and resolves the risk to run into unaligned 64-bit accesses. >> >> Based on original patch by Lokesh Vulta. >> >> Signed-off-by: Jan Kiszka <jan.kiszka at siemens.com> > > Thanks for the patch. I guess both R5 SPL and A53 SPL caches gets enabled with > this patch? I strongly suspect so: I didn't find anything in your original patch that prevented that, nor did I add anything in this one. Sorry, I wasn't able to test on an EVM yet, and our target does not use U-Boot for the R5. Would be appreciated if you could throw this on both affected EVMs (of which I only have one anyway). Jan > > Thanks and regards, > Lokesh > >> --- >> arch/arm/mach-k3/am6_init.c | 1 + >> arch/arm/mach-k3/common.c | 35 +++++++++++++++++++++++++++++++++++ >> arch/arm/mach-k3/common.h | 1 + >> arch/arm/mach-k3/j721e_init.c | 1 + >> board/ti/am65x/evm.c | 2 ++ >> 5 files changed, 40 insertions(+) >> >> diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c >> index b692806352..586f5c022e 100644 >> --- a/arch/arm/mach-k3/am6_init.c >> +++ b/arch/arm/mach-k3/am6_init.c >> @@ -197,6 +197,7 @@ void board_init_f(ulong dummy) >> if (ret) >> panic("DRAM init failed: %d\n", ret); >> #endif >> + spl_enable_dcache(); >> } >> >> u32 spl_mmc_boot_mode(const u32 boot_device) >> diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c >> index 80dfa5f0fd..a94e054491 100644 >> --- a/arch/arm/mach-k3/common.c >> +++ b/arch/arm/mach-k3/common.c >> @@ -406,3 +406,38 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) >> } >> } >> } >> + >> +void spl_enable_dcache(void) >> +{ >> +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) >> + phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; >> + >> + dram_init_banksize(); >> + >> + /* reserve TLB table */ >> + gd->arch.tlb_size = PGTABLE_SIZE; >> + >> + ram_top += get_effective_memsize(); >> + /* keep ram_top in the 32-bit address space */ >> + if (ram_top >= 0x100000000) >> + ram_top = (phys_addr_t) 0x100000000; >> + >> + gd->arch.tlb_addr = ram_top - gd->arch.tlb_size; >> + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, >> + gd->arch.tlb_addr + gd->arch.tlb_size); >> + >> + dcache_enable(); >> +#endif >> +} >> + >> +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) >> +void spl_board_prepare_for_boot(void) >> +{ >> + dcache_disable(); >> +} >> + >> +void spl_board_prepare_for_boot_linux(void) >> +{ >> + dcache_disable(); >> +} >> +#endif >> diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h >> index 57682e1973..94cdcb56ad 100644 >> --- a/arch/arm/mach-k3/common.h >> +++ b/arch/arm/mach-k3/common.h >> @@ -27,3 +27,4 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size); >> void start_non_linux_remote_cores(void); >> int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr); >> void k3_sysfw_print_ver(void); >> +void spl_enable_dcache(void); >> diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c >> index 71fc20c30b..3ffdb6f258 100644 >> --- a/arch/arm/mach-k3/j721e_init.c >> +++ b/arch/arm/mach-k3/j721e_init.c >> @@ -221,6 +221,7 @@ void board_init_f(ulong dummy) >> if (ret) >> panic("DRAM init failed: %d\n", ret); >> #endif >> + spl_enable_dcache(); >> } >> >> u32 spl_mmc_boot_mode(const u32 boot_device) >> diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c >> index a610879424..2da7db9f09 100644 >> --- a/board/ti/am65x/evm.c >> +++ b/board/ti/am65x/evm.c >> @@ -69,11 +69,13 @@ int dram_init_banksize(void) >> /* Bank 0 declares the memory available in the DDR low region */ >> gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; >> gd->bd->bi_dram[0].size = 0x80000000; >> + gd->ram_size = 0x80000000; >> >> #ifdef CONFIG_PHYS_64BIT >> /* Bank 1 declares the memory available in the DDR high region */ >> gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; >> gd->bd->bi_dram[1].size = 0x80000000; >> + gd->ram_size = 0x100000000; >> #endif >> >> return 0; >>
On 19.05.20 08:24, Jan Kiszka wrote: > On 19.05.20 08:18, Lokesh Vutla wrote: >> Hi Jan, >> >> On 18/05/20 11:27 am, Jan Kiszka wrote: >>> From: Jan Kiszka <jan.kiszka at siemens.com> >>> >>> Add support for enabling dcache already in SPL. It accelerates the boot >>> and resolves the risk to run into unaligned 64-bit accesses. >>> >>> Based on original patch by Lokesh Vulta. >>> >>> Signed-off-by: Jan Kiszka <jan.kiszka at siemens.com> >> >> Thanks for the patch. I guess both R5 SPL and A53 SPL caches gets >> enabled with >> this patch? > > I strongly suspect so: I didn't find anything in your original patch > that prevented that, nor did I add anything in this one. > > Sorry, I wasn't able to test on an EVM yet, and our target does not use > U-Boot for the R5. Would be appreciated if you could throw this on both > affected EVMs (of which I only have one anyway). > Just ran this successfully on the am654-evm. Jan
On 19/05/20 12:30 pm, Jan Kiszka wrote: > On 19.05.20 08:24, Jan Kiszka wrote: >> On 19.05.20 08:18, Lokesh Vutla wrote: >>> Hi Jan, >>> >>> On 18/05/20 11:27 am, Jan Kiszka wrote: >>>> From: Jan Kiszka <jan.kiszka at siemens.com> >>>> >>>> Add support for enabling dcache already in SPL. It accelerates the boot >>>> and resolves the risk to run into unaligned 64-bit accesses. >>>> >>>> Based on original patch by Lokesh Vulta. >>>> >>>> Signed-off-by: Jan Kiszka <jan.kiszka at siemens.com> >>> >>> Thanks for the patch. I guess both R5 SPL and A53 SPL caches gets enabled with >>> this patch? >> >> I strongly suspect so: I didn't find anything in your original patch that >> prevented that, nor did I add anything in this one. >> >> Sorry, I wasn't able to test on an EVM yet, and our target does not use U-Boot >> for the R5. Would be appreciated if you could throw this on both affected EVMs >> (of which I only have one anyway). >> > > Just ran this successfully on the am654-evm. I was able to boot on J721e-evm as well. Initially I was worried that caches were not enabled for SRAM when running R5 SPL. But MPU regions are taking care of it. Acked-by: Lokesh Vutla <lokeshvutla at ti.com> Will merge this patch soon. Thanks and regards, Lokesh
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index b692806352..586f5c022e 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -197,6 +197,7 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif + spl_enable_dcache(); } u32 spl_mmc_boot_mode(const u32 boot_device) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 80dfa5f0fd..a94e054491 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -406,3 +406,38 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) } } } + +void spl_enable_dcache(void) +{ +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) + phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; + + dram_init_banksize(); + + /* reserve TLB table */ + gd->arch.tlb_size = PGTABLE_SIZE; + + ram_top += get_effective_memsize(); + /* keep ram_top in the 32-bit address space */ + if (ram_top >= 0x100000000) + ram_top = (phys_addr_t) 0x100000000; + + gd->arch.tlb_addr = ram_top - gd->arch.tlb_size; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + dcache_enable(); +#endif +} + +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +void spl_board_prepare_for_boot(void) +{ + dcache_disable(); +} + +void spl_board_prepare_for_boot_linux(void) +{ + dcache_disable(); +} +#endif diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 57682e1973..94cdcb56ad 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -27,3 +27,4 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size); void start_non_linux_remote_cores(void); int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr); void k3_sysfw_print_ver(void); +void spl_enable_dcache(void); diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 71fc20c30b..3ffdb6f258 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -221,6 +221,7 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif + spl_enable_dcache(); } u32 spl_mmc_boot_mode(const u32 boot_device) diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index a610879424..2da7db9f09 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -69,11 +69,13 @@ int dram_init_banksize(void) /* Bank 0 declares the memory available in the DDR low region */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; gd->bd->bi_dram[1].size = 0x80000000; + gd->ram_size = 0x100000000; #endif return 0;