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[23.128.96.18]) by mx.google.com with ESMTP id b7si2252324edq.546.2020.07.23.08.26.58; Thu, 23 Jul 2020 08:26:59 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZibBjkqe; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729568AbgGWP06 (ORCPT + 6 others); Thu, 23 Jul 2020 11:26:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728725AbgGWP05 (ORCPT ); Thu, 23 Jul 2020 11:26:57 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53A36C0619DC for ; Thu, 23 Jul 2020 08:26:57 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id r4so2608168wrx.9 for ; Thu, 23 Jul 2020 08:26:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8/f3+aWQD6jv0BacPrlT71wq4KzB+QZIhzZYF2sQn5E=; b=ZibBjkqePpOt6wdwejuWLwFNSiWg1V3RghiCXkrwZ2zbCXKNFcgMngbifiPD7ZtIaV CFUA1mvy/F3qhrX9YIPJSSK7Q8Fo7PxR7DTTvYzuxwE5/norGhp3rzrM3aKgsreCQxpS gKcQCwfO7PqBQOJ+9jYGEOZzc8BbHwaX8G89pODVWQCyEX5sLYkDzrgtxzOiKQ29i/gQ SIGKnrd/qVDvMLdd8i4EmC2OX//b5pZBDRK5adLOz/qQBYM2Cndq6lSgFo+lJB4ATZf5 R3UnYH8RMDu4xBC++zoGIK5FvqM07FPesWZRz/y0saCEQPXrBPpDcKcCemI+MZEn06lQ QVeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8/f3+aWQD6jv0BacPrlT71wq4KzB+QZIhzZYF2sQn5E=; b=G7GhX/JSG2W3DTxQdfaAayJAy6obHtetqVsgip8xFRFL/fn6rG8FGxUwwiJw9A/1VP yvdeXFjWoOALEmNk8EwN0SeckPKw3Py7DFxmsFSKd1GyCmR7tnQhJwB70RPwLJDKXLyF U9rel4ewTUqBouF49rIHcCxPzQnkvIDbT912c8eE7JHITQSsw8MoGFTWegGFwAVREc9K cuNbQWKxLAN+ioXFYgPoAqnC9UB7vwBaGstdRc2hnviTrAJF9ofnIX4Xus4PfirJSnpP jr0RJl8HXiBqC0QuNnZ1dvYE0fmrcs2Svdddyg+XRJeVQsu6AYcCtW7dnjFaJBj7pzdC 1o0w== X-Gm-Message-State: AOAM531t1BU4OF+VhAe3wUnaV0uIEzXp4BT9EMO6HXCvgABQXAAJqL7c nQIER/It4EbPiS2ASII37L9i3Q== X-Received: by 2002:a5d:4e92:: with SMTP id e18mr4588679wru.107.1595518015861; Thu, 23 Jul 2020 08:26:55 -0700 (PDT) Received: from mai.imgcgcw.net ([2a01:e34:ed2f:f020:dca7:8d30:33fa:daac]) by smtp.gmail.com with ESMTPSA id g145sm5963491wmg.23.2020.07.23.08.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2020 08:26:55 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: Alexandre Belloni , Rob Herring , Rob Herring , Nicolas Ferre , Ludovic Desroches , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Microchip (AT91) SoC support), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 02/16] dt-bindings: microchip: atmel, at91rm9200-tcb: add sama5d2 compatible Date: Thu, 23 Jul 2020 17:26:22 +0200 Message-Id: <20200723152639.639771-2-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200723152639.639771-1-daniel.lezcano@linaro.org> References: <1b1122f4-bce9-f349-e602-ed8e14cbb501@linaro.org> <20200723152639.639771-1-daniel.lezcano@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Alexandre Belloni The sama5d2 TC block TIMER_CLOCK1 is different from the at91sam9x5 one. Instead of being MCK / 2, it is the TCB GCLK. Reviewed-by: Rob Herring Signed-off-by: Alexandre Belloni Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200710230813.1005150-3-alexandre.belloni@bootlin.com --- .../soc/microchip/atmel,at91rm9200-tcb.yaml | 42 +++++++++++++++---- 1 file changed, 33 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml index 9d680e0b9109..d226fd7d5258 100644 --- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml @@ -19,6 +19,7 @@ properties: - enum: - atmel,at91rm9200-tcb - atmel,at91sam9x5-tcb + - atmel,sama5d2-tcb - const: simple-mfd - const: syscon @@ -36,15 +37,6 @@ properties: description: List of clock names. Always includes t0_clk and slow clk. Also includes t1_clk and t2_clk if a clock per channel is available. - oneOf: - - items: - - const: t0_clk - - const: slow_clk - - items: - - const: t0_clk - - const: t1_clk - - const: t2_clk - - const: slow_clk minItems: 2 maxItems: 4 @@ -75,6 +67,38 @@ patternProperties: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + const: atmel,sama5d2-tcb + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: t0_clk + - const: gclk + - const: slow_clk + else: + properties: + clocks: + minItems: 2 + maxItems: 4 + clock-names: + oneOf: + - items: + - const: t0_clk + - const: slow_clk + - items: + - const: t0_clk + - const: t1_clk + - const: t2_clk + - const: slow_clk + required: - compatible - reg