[Xen-devel] xen/arm: Save/restore GICH_VMCR on domain context switch

Message ID 1392731901-20233-1-git-send-email-julien.grall@linaro.org
State Accepted
Headers show

Commit Message

Julien Grall Feb. 18, 2014, 1:58 p.m.
GICH_VMCR register contains alias to important bits of GICV interface such as:
    - priority mask of the CPU
    - EOImode
    - ...

We were safe because Linux guest always use the same value for this bits.
When new guests will handle priority or change EOI mode, VCPU interrupt
management will be in a wrong state.

Signed-off-by: Julien Grall <julien.grall@linaro.org>
Cc: George Dunlap <george.dunlap@citrix.com>

---
    This is a bug fix for Xen 4.4. Without this patch we can't support guest
    that doesn't have the same behavior as Linux to handle GICC interface.
    theses bits are not modified by them.
---
 xen/arch/arm/gic.c |    2 ++
 1 file changed, 2 insertions(+)

Comments

Ian Campbell Feb. 18, 2014, 2:51 p.m. | #1
On Tue, 2014-02-18 at 13:58 +0000, Julien Grall wrote:
> GICH_VMCR register contains alias to important bits of GICV interface such as:
>     - priority mask of the CPU
>     - EOImode
>     - ...
> 
> We were safe because Linux guest always use the same value for this bits.
> When new guests will handle priority or change EOI mode, VCPU interrupt
> management will be in a wrong state.
> 
> Signed-off-by: Julien Grall <julien.grall@linaro.org>
> Cc: George Dunlap <george.dunlap@citrix.com>

Acked-by: Ian Campbell <ian.campbell@citrix.com>

> ---
>     This is a bug fix for Xen 4.4. Without this patch we can't support guest
>     that doesn't have the same behavior as Linux to handle GICC interface.
>     theses bits are not modified by them.

I'd say we pretty much have to take this -- otherwise some guest can
break things for everyone else by writing to GICC registers.

I've had a look at the GICH register list and I think we correctly
switch everything else.

Ian.

> ---
>  xen/arch/arm/gic.c |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index 62294ac..51e5990 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -107,6 +107,7 @@ void gic_save_state(struct vcpu *v)
>          v->arch.gic_lr[i] = GICH[GICH_LR + i];
>      v->arch.lr_mask = this_cpu(lr_mask);
>      v->arch.gic_apr = GICH[GICH_APR];
> +    v->arch.gic_vmcr = GICH[GICH_VMCR];
>      /* Disable until next VCPU scheduled */
>      GICH[GICH_HCR] = 0;
>      isb();
> @@ -123,6 +124,7 @@ void gic_restore_state(struct vcpu *v)
>      for ( i=0; i<nr_lrs; i++)
>          GICH[GICH_LR + i] = v->arch.gic_lr[i];
>      GICH[GICH_APR] = v->arch.gic_apr;
> +    GICH[GICH_VMCR] = v->arch.gic_vmcr;
>      GICH[GICH_HCR] = GICH_HCR_EN;
>      isb();
>

Patch

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 62294ac..51e5990 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -107,6 +107,7 @@  void gic_save_state(struct vcpu *v)
         v->arch.gic_lr[i] = GICH[GICH_LR + i];
     v->arch.lr_mask = this_cpu(lr_mask);
     v->arch.gic_apr = GICH[GICH_APR];
+    v->arch.gic_vmcr = GICH[GICH_VMCR];
     /* Disable until next VCPU scheduled */
     GICH[GICH_HCR] = 0;
     isb();
@@ -123,6 +124,7 @@  void gic_restore_state(struct vcpu *v)
     for ( i=0; i<nr_lrs; i++)
         GICH[GICH_LR + i] = v->arch.gic_lr[i];
     GICH[GICH_APR] = v->arch.gic_apr;
+    GICH[GICH_VMCR] = v->arch.gic_vmcr;
     GICH[GICH_HCR] = GICH_HCR_EN;
     isb();