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([185.25.64.249]) by mx.google.com with ESMTPSA id y47sm70546300eel.14.2014.02.18.05.58.28 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Feb 2014 05:58:28 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 18 Feb 2014 13:58:21 +0000 Message-Id: <1392731901-20233-1-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com, George Dunlap Subject: [Xen-devel] [PATCH] xen/arm: Save/restore GICH_VMCR on domain context switch X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.169 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: GICH_VMCR register contains alias to important bits of GICV interface such as: - priority mask of the CPU - EOImode - ... We were safe because Linux guest always use the same value for this bits. When new guests will handle priority or change EOI mode, VCPU interrupt management will be in a wrong state. Signed-off-by: Julien Grall Cc: George Dunlap Acked-by: Ian Campbell --- This is a bug fix for Xen 4.4. Without this patch we can't support guest that doesn't have the same behavior as Linux to handle GICC interface. theses bits are not modified by them. --- xen/arch/arm/gic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 62294ac..51e5990 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -107,6 +107,7 @@ void gic_save_state(struct vcpu *v) v->arch.gic_lr[i] = GICH[GICH_LR + i]; v->arch.lr_mask = this_cpu(lr_mask); v->arch.gic_apr = GICH[GICH_APR]; + v->arch.gic_vmcr = GICH[GICH_VMCR]; /* Disable until next VCPU scheduled */ GICH[GICH_HCR] = 0; isb(); @@ -123,6 +124,7 @@ void gic_restore_state(struct vcpu *v) for ( i=0; iarch.gic_lr[i]; GICH[GICH_APR] = v->arch.gic_apr; + GICH[GICH_VMCR] = v->arch.gic_vmcr; GICH[GICH_HCR] = GICH_HCR_EN; isb();