| Message ID | 20200916132000.1850-6-manivannan.sadhasivam@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Add PCIe support for SM8250 SoC | expand |
s/Harcode/Hardcode/ (in subject) Also fix subject format as for 4/5. On Wed, Sep 16, 2020 at 06:50:00PM +0530, Manivannan Sadhasivam wrote: > Hardcode the PCIe config SID table value. This is needed to avoid random > MHI failure observed during reboot on SM8250. > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > [mani: stripped out unnecessary settings and ported for upstream] > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index ca8ad354e09d..50748016ce96 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -57,6 +57,7 @@ > #define PCIE20_PARF_SID_OFFSET 0x234 > #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C > #define PCIE20_PARF_DEVICE_TYPE 0x1000 > +#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000 > > #define PCIE20_ELBI_SYS_CTRL 0x04 > #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) > @@ -1290,6 +1291,9 @@ static int qcom_pcie_host_init(struct pcie_port *pp) > if (ret) > goto err; > > + writel(0x0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N); > + writel(0x01000100, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + 0x054); > + > return 0; > err: > qcom_ep_reset_assert(pcie); > -- > 2.17.1 >
On Wed 16 Sep 08:20 CDT 2020, Manivannan Sadhasivam wrote: > Hardcode the PCIe config SID table value. This is needed to avoid random > MHI failure observed during reboot on SM8250. > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > [mani: stripped out unnecessary settings and ported for upstream] > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index ca8ad354e09d..50748016ce96 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -57,6 +57,7 @@ > #define PCIE20_PARF_SID_OFFSET 0x234 > #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C > #define PCIE20_PARF_DEVICE_TYPE 0x1000 > +#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000 > > #define PCIE20_ELBI_SYS_CTRL 0x04 > #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) > @@ -1290,6 +1291,9 @@ static int qcom_pcie_host_init(struct pcie_port *pp) > if (ret) > goto err; > > + writel(0x0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N); > + writel(0x01000100, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + 0x054); This needs to be properly implemented. The mechanism at hand is responsible for mapping BDFs by the means of a BDF->SID hash table. Per the downstream kernel the hash is 256 entries of 32 bits registers. The slot is selected by taking the crc8() of the BDF (in big endian) and in that slot encode the BDF in the upper 16 bits, followed by the SID (relative to the first SID of the controller) in the next 8 and finally the index of the next entry in cases of collisions. Also like the downstream kernel you can extract this information from the iommu-map property. But note that the last cell in the iommu-map is "length", not mask as in the typical iommus property - so you would need to install "length" entries in the hash table, for each iommu-map. Finally, this was first introduced in SM8150, so it can not be done unconditionally in qcom_pcie_host_init(). The previous hardware used a different mechanism for configuring this information. Regards, Bjorn > + > return 0; > err: > qcom_ep_reset_assert(pcie); > -- > 2.17.1 >
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index ca8ad354e09d..50748016ce96 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -57,6 +57,7 @@ #define PCIE20_PARF_SID_OFFSET 0x234 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C #define PCIE20_PARF_DEVICE_TYPE 0x1000 +#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000 #define PCIE20_ELBI_SYS_CTRL 0x04 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) @@ -1290,6 +1291,9 @@ static int qcom_pcie_host_init(struct pcie_port *pp) if (ret) goto err; + writel(0x0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N); + writel(0x01000100, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + 0x054); + return 0; err: qcom_ep_reset_assert(pcie);