| Message ID | 20200817162309.362032-1-robdclark@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm/gpu: make ringbuffer readonly | expand |
On Mon, Aug 17, 2020 at 09:23:09AM -0700, Rob Clark wrote: > From: Rob Clark <robdclark@chromium.org> > > The GPU has no business writing into the ringbuffer, let's make it > readonly to the GPU. Yep. There are some additional things we can do in the a6xx family to make this even more robust but for the vast majority of targets out in this world this is a good and necessary fix. Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> > Fixes: 7198e6b03155 ("drm/msm: add a3xx gpu support") > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > drivers/gpu/drm/msm/msm_ringbuffer.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c > index e397c44cc011..39ecb5a18431 100644 > --- a/drivers/gpu/drm/msm/msm_ringbuffer.c > +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c > @@ -27,7 +27,8 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, > ring->id = id; > > ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ, > - MSM_BO_WC, gpu->aspace, &ring->bo, &ring->iova); > + MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &ring->bo, > + &ring->iova); > > if (IS_ERR(ring->start)) { > ret = PTR_ERR(ring->start); > -- > 2.26.2 >
diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c index e397c44cc011..39ecb5a18431 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.c +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c @@ -27,7 +27,8 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, ring->id = id; ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ, - MSM_BO_WC, gpu->aspace, &ring->bo, &ring->iova); + MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &ring->bo, + &ring->iova); if (IS_ERR(ring->start)) { ret = PTR_ERR(ring->start);