tty: serial: qcom_geni_serial: Remove the UART frequency table

Use clk_round_rate() API to find a frequency that will work with the
requested baud rate. With this we can avoid updating the table each time
we add a new frquency to the table. We can just call clk_round_rate() and
make sure it is evenly divisible by the requested rate and then it will be
the same as before.

Signed-off-by: satya priya <skakit@codeaurora.org>
---
 drivers/tty/serial/qcom_geni_serial.c | 32 +++++++++-----------------------
 1 file changed, 9 insertions(+), 23 deletions(-)

Quoting satya priya (2020-08-11 22:48:48)
> diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
> index 3aa29d2..312daa24 100644
> --- a/drivers/tty/serial/qcom_geni_serial.c
> +++ b/drivers/tty/serial/qcom_geni_serial.c
> @@ -941,30 +935,22 @@ static int qcom_geni_serial_startup(struct uart_port *uport)
>         return 0;
>  }
>  
> -static unsigned long get_clk_cfg(unsigned long clk_freq)
> -{
> -       int i;
> -
> -       for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
> -               if (!(root_freq[i] % clk_freq))
> -                       return root_freq[i];
> -       }
> -       return 0;
> -}
> -
> -static unsigned long get_clk_div_rate(unsigned int baud,
> -                       unsigned int sampling_rate, unsigned int *clk_div)
> +static unsigned long get_clk_div_rate(const struct geni_se *se,
> +                       unsigned int baud, unsigned int sampling_rate,
> +                       unsigned int *clk_div)
>  {
>         unsigned long ser_clk;
>         unsigned long desired_clk;
> +       long actual_clk;
>  
>         desired_clk = baud * sampling_rate;
> -       ser_clk = get_clk_cfg(desired_clk);
> -       if (!ser_clk) {
> +       actual_clk = clk_round_rate(se->clk, desired_clk);
> +       if (actual_clk % desired_clk != 0) {

The logic isn't the same. Is that a concern? Before we would loop
through all the frequencies this driver knew about and try to find a
frequency that evenly divides by the 'desired_clk'. With this patch
we'll do that calculation exactly once, and ask the clk driver what rate
can be achieved if we call clk_set_rate() with 'desired_clk' as the
argument.

Maybe we need to loop and call clk_round_rate() with 'desired_clk <<= 1'
until it overflows or reaches some limit?

>                 pr_err("%s: Can't find matching DFS entry for baud %d\n",
>                                                                 __func__, baud);
> -               return ser_clk;
> +               return 0;
>         }
> +       ser_clk = actual_clk;
>  
>         *clk_div = ser_clk / desired_clk;
>         return ser_clk;