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[4/4] ALSA: hda - fix CONTROLLER_IN_GPU macro name

Message ID 20200921141741.2983072-5-kai.vehmanen@linux.intel.com
State Accepted
Commit 534ad9afb19b5ac810a5e1c638f371e81e0c1ed6
Headers show
Series ALSA: hda - add Intel DG1 support | expand

Commit Message

Kai Vehmanen Sept. 21, 2020, 2:17 p.m. UTC 
The CONTROLLER_IN_GPU() macro has different semantics than
the similarly named macro in hda_intel.c. The name is also
misleading as the macro is used to apply a Intel HSW/BDW
programming logic for HDA controller clock configuration.
Rename macro to reflect the actual implementation.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
---
 sound/hda/hdac_i915.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/sound/hda/hdac_i915.c b/sound/hda/hdac_i915.c
index 50b2c1db429b..d236e497435d 100644
--- a/sound/hda/hdac_i915.c
+++ b/sound/hda/hdac_i915.c
@@ -13,7 +13,7 @@ 
 
 static struct completion bind_complete;
 
-#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
+#define IS_HSW_CONTROLLER(pci) (((pci)->device == 0x0a0c) || \
 				((pci)->device == 0x0c0c) || \
 				((pci)->device == 0x0d0c) || \
 				((pci)->device == 0x160c))
@@ -41,7 +41,7 @@  void snd_hdac_i915_set_bclk(struct hdac_bus *bus)
 
 	if (!acomp || !acomp->ops || !acomp->ops->get_cdclk_freq)
 		return; /* only for i915 binding */
-	if (!CONTROLLER_IN_GPU(pci))
+	if (!IS_HSW_CONTROLLER(pci))
 		return; /* only HSW/BDW */
 
 	cdclk_freq = acomp->ops->get_cdclk_freq(acomp->dev);