diff mbox

target-arm: Add ARM_CP_IO notation to PMCR reginfo

Message ID 1394908291-16546-1-git-send-email-peter.maydell@linaro.org
State Accepted
Headers show

Commit Message

Peter Maydell March 15, 2014, 6:31 p.m. UTC
Now that the PMCR writefn makes timer accesses, its reginfo needs
the ARM_CP_IO flag, so that icount mode works correctly. (Fixes
the bug accidentally introduced in commit 7c2cb42b).

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Laurent Desnogues March 15, 2014, 6:38 p.m. UTC | #1
On Sat, Mar 15, 2014 at 7:31 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> Now that the PMCR writefn makes timer accesses, its reginfo needs
> the ARM_CP_IO flag, so that icount mode works correctly. (Fixes
> the bug accidentally introduced in commit 7c2cb42b).
>
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Thanks,

Laurent

> ---
>  target-arm/helper.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index aa5f22d..e895879 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1983,6 +1983,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>          ARMCPRegInfo pmcr = {
>              .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
>              .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
> +            .type = ARM_CP_IO,
>              .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
>              .accessfn = pmreg_access, .writefn = pmcr_write,
>              .raw_writefn = raw_write,
> --
> 1.9.0
>
diff mbox

Patch

diff --git a/target-arm/helper.c b/target-arm/helper.c
index aa5f22d..e895879 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1983,6 +1983,7 @@  void register_cp_regs_for_features(ARMCPU *cpu)
         ARMCPRegInfo pmcr = {
             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
             .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
+            .type = ARM_CP_IO,
             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
             .accessfn = pmreg_access, .writefn = pmcr_write,
             .raw_writefn = raw_write,