diff mbox

[Xen-devel,PATCH=v3,1/8] xen: arm: map memory as inner shareable.

Message ID 1395077816.18221.53.camel@kazak.uk.xensource.com
State Accepted
Commit 8200daed053bc7f3dca4ee5b42d9f84934b998d7
Headers show

Commit Message

Ian Campbell March 17, 2014, 5:36 p.m. UTC 
On Mon, 2014-03-17 at 15:17 +0000, Julien Grall wrote:
> AFAIU, you are also modifying P2M attributes.

True. This patch (#9/8) works for me:

---------8<---------------------

From 573bb9d531e47b50f02767ed363ad3e5df6be2a7 Mon Sep 17 00:00:00 2001
From: Ian Campbell <ian.campbell@citrix.com>
Date: Mon, 17 Mar 2014 17:27:40 +0000
Subject: [PATCH] xen: arm: make stage 2 page tables walks inner-shareable

The comment was previously incorrect and indicated that these mappings were
unshared (00) when in reality the register was set for outer-shareable (01).

Clarify ORGN0/IRGN0 in the comments while at it.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
 xen/arch/arm/mm.c |    7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Comments

Julien Grall March 18, 2014, 1:47 p.m. UTC | #1 
On 03/17/2014 05:36 PM, Ian Campbell wrote:
> On Mon, 2014-03-17 at 15:17 +0000, Julien Grall wrote:
>> AFAIU, you are also modifying P2M attributes.
> 
> True. This patch (#9/8) works for me:
> 
> ---------8<---------------------
> 
> From 573bb9d531e47b50f02767ed363ad3e5df6be2a7 Mon Sep 17 00:00:00 2001
> From: Ian Campbell <ian.campbell@citrix.com>
> Date: Mon, 17 Mar 2014 17:27:40 +0000
> Subject: [PATCH] xen: arm: make stage 2 page tables walks inner-shareable
> 
> The comment was previously incorrect and indicated that these mappings were
> unshared (00) when in reality the register was set for outer-shareable (01).
> 
> Clarify ORGN0/IRGN0 in the comments while at it.
> 
> Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>

BTW, do you have a git branch with this patch series applied? I'd like
to rebase my SMMU drivers code on top of it.

Regards,
Ian Campbell March 18, 2014, 4:12 p.m. UTC | #2 
On Tue, 2014-03-18 at 13:47 +0000, Julien Grall wrote:
> On 03/17/2014 05:36 PM, Ian Campbell wrote:
> > On Mon, 2014-03-17 at 15:17 +0000, Julien Grall wrote:
> >> AFAIU, you are also modifying P2M attributes.
> > 
> > True. This patch (#9/8) works for me:
> > 
> > ---------8<---------------------
> > 
> > From 573bb9d531e47b50f02767ed363ad3e5df6be2a7 Mon Sep 17 00:00:00 2001
> > From: Ian Campbell <ian.campbell@citrix.com>
> > Date: Mon, 17 Mar 2014 17:27:40 +0000
> > Subject: [PATCH] xen: arm: make stage 2 page tables walks inner-shareable
> > 
> > The comment was previously incorrect and indicated that these mappings were
> > unshared (00) when in reality the register was set for outer-shareable (01).
> > 
> > Clarify ORGN0/IRGN0 in the comments while at it.
> > 
> > Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
> Acked-by: Julien Grall <julien.grall@linaro.org>

Thanks, I pushed all 8+1 patches.

Ian.
diff mbox

Patch

diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index e9b3f34..6f1408b 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -378,16 +378,17 @@  void __init arch_init_memory(void)
 void __cpuinit setup_virt_paging(void)
 {
     /* Setup Stage 2 address translation */
-    /* SH0=00, ORGN0=IRGN0=01
+    /* SH0=11 (Inner-shareable)
+     * ORGN0=IRGN0=01 (Normal memory, Write-Back Write-Allocate Cacheable)
      * SL0=01 (Level-1)
      * ARVv7: T0SZ=(1)1000 = -8 (32-(-8) = 40 bit physical addresses)
      * ARMv8: T0SZ=01 1000 = 24 (64-24   = 40 bit physical addresses)
      *        PS=010 == 40 bits
      */
 #ifdef CONFIG_ARM_32
-    WRITE_SYSREG32(0x80002558, VTCR_EL2);
+    WRITE_SYSREG32(0x80003558, VTCR_EL2);
 #else
-    WRITE_SYSREG32(0x80022558, VTCR_EL2);
+    WRITE_SYSREG32(0x80023558, VTCR_EL2);
 #endif
     isb();
 }