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[2001:770:15f::2]) by mx.google.com with ESMTPS id wm8si10757000wjb.173.2014.03.17.14.55.50 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Mar 2014 14:55:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:770:15f::2 as permitted sender) client-ip=2001:770:15f::2; Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WPfVB-0006kB-46; Mon, 17 Mar 2014 21:55:21 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WPfV8-0008Bn-K1; Mon, 17 Mar 2014 21:55:18 +0000 Received: from relais.videotron.ca ([24.201.245.36]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WPfV6-0008BB-Ox for linux-arm-kernel@lists.infradead.org; Mon, 17 Mar 2014 21:55:17 +0000 MIME-version: 1.0 Received: from yoda.home ([66.130.143.177]) by VL-VM-MR001.ip.videotron.ca (Oracle Communications Messaging Exchange Server 7u4-22.01 64bit (built Apr 21 2011)) with ESMTP id <0N2L00M28OV79BB1@VL-VM-MR001.ip.videotron.ca> for linux-arm-kernel@lists.infradead.org; Mon, 17 Mar 2014 17:54:43 -0400 (EDT) Received: from xanadu.home (xanadu.home [192.168.2.2]) by yoda.home (Postfix) with ESMTPSA id EDC3D2DA05FA; Mon, 17 Mar 2014 17:54:42 -0400 (EDT) Date: Mon, 17 Mar 2014 17:54:42 -0400 (EDT) From: Nicolas Pitre To: Russell King - ARM Linux Subject: Re: PL310 errata workarounds In-reply-to: <20140317211455.GM21483@n2100.arm.linux.org.uk> Message-id: References: <20140314144835.GP21483@n2100.arm.linux.org.uk> <20140314150110.GQ21483@n2100.arm.linux.org.uk> <20140316115207.GW21483@n2100.arm.linux.org.uk> <20140317153738.GB21483@n2100.arm.linux.org.uk> <20140317172943.GI24070@arm.com> <20140317194440.GG21483@n2100.arm.linux.org.uk> <20140317211455.GM21483@n2100.arm.linux.org.uk> User-Agent: Alpine 2.11 (LFD 23 2013-08-11) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140317_175516_841653_05DDB549 X-CRM114-Status: GOOD ( 24.56 ) X-Spam-Score: -1.2 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [24.201.245.36 listed in list.dnswl.org] 0.7 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Catalin Marinas , Will Deacon , Santosh Shilimkar , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: nicolas.pitre@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 On Mon, 17 Mar 2014, Russell King - ARM Linux wrote: > On Mon, Mar 17, 2014 at 05:09:46PM -0400, Nicolas Pitre wrote: > > L2 is normally a per cluster resource. It is flushed by the last man > > standing when no other CPUs might contend for the L2 controller. And if > > the outer cache is shared by multiple clusters then some additional > > handling (such as "last cluster standing") would need to be implemented. > > > > Clearly this outer_cache_flush() call is just a hint if someone were to > > copy that file to write their own backend. If it is causing problems > > then it should just be removed altogether. No platforms with MCPM that > > I know of have an actual outer cache at the moment. And certainly not > > the platform where dcscb.c is used. > > This sounds to me like an invitation to kill it :) Killing it off > would be good, though maybe a comment should be left behind at this > site? > > As you're the most familiar with this code, I'd prefer to commit a > patch from you rather than just deleting the reference myself. OK, what about the following: ----- >8 Subject: ARM: dcscb.c: remove actual call to outer_flush_all() Strictly speaking this call is a no-op on the platform where dcscb.c is used since it only has architected caches. The call was there as a hint to people who would be inspired by this code to write their own backend but the hint might not always be correct. For example, if a PL310 were to be used this wouldn't be safe to call the regular outer_flush_all() anyway as it makes use of atomic instructions for locking which cannot be assumed to still be operational after v7_exit_coherency_flush() has returned. Given no other CPUs (in the cluster) should be running at that point then standard concurrency concerns wouldn't apply. So let's simply kill this call for now and enhance the existing comment. Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c index 14d4996887..e717515999 100644 --- a/arch/arm/mach-vexpress/dcscb.c +++ b/arch/arm/mach-vexpress/dcscb.c @@ -137,11 +137,10 @@ static void dcscb_power_down(void) v7_exit_coherency_flush(all); /* - * This is a harmless no-op. On platforms with a real - * outer cache this might either be needed or not, - * depending on where the outer cache sits. + * A full outer cache flush could be needed at this point + * on platforms with a real outer cache. This might either + * be needed or not depending on where the outer cache sits. */ - outer_flush_all(); /* * Disable cluster-level coherency by masking