diff mbox series

[2/3] drm/exynos: Scale the DSIM PHY HFP/HBP/HSA to lanes and bpp

Message ID 20201005134250.527153-2-marex@denx.de
State New
Headers show
Series None | expand

Commit Message

Marek Vasut Oct. 5, 2020, 1:42 p.m. UTC
The value programmed into horizontal porch and sync registers must be
scaled to the correct number of DSI lanes and bpp, make it so.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Guido Günther <agx@sigxcpu.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Michael Tretter <m.tretter@pengutronix.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
To: dri-devel@lists.freedesktop.org
--
NOTE: This depends on https://patchwork.kernel.org/project/dri-devel/list/?series=347439
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Comments

Frieder Schrempf Dec. 10, 2020, 3:01 p.m. UTC | #1
On 05.10.20 15:42, Marek Vasut wrote:
> The value programmed into horizontal porch and sync registers must be

> scaled to the correct number of DSI lanes and bpp, make it so.

> 

> Signed-off-by: Marek Vasut <marex@denx.de>

> Cc: Fabio Estevam <festevam@gmail.com>

> Cc: Guido Günther <agx@sigxcpu.org>

> Cc: Jaehoon Chung <jh80.chung@samsung.com>

> Cc: Lucas Stach <l.stach@pengutronix.de>

> Cc: Marek Szyprowski <m.szyprowski@samsung.com>

> Cc: Michael Tretter <m.tretter@pengutronix.de>

> Cc: NXP Linux Team <linux-imx@nxp.com>

> Cc: Shawn Guo <shawnguo@kernel.org>

> Cc: linux-arm-kernel@lists.infradead.org

> Cc: linux-samsung-soc@vger.kernel.org

> To: dri-devel@lists.freedesktop.org

> --

> NOTE: This depends on https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.kernel.org%2Fproject%2Fdri-devel%2Flist%2F%3Fseries%3D347439&amp;data=02%7C01%7Cfrieder.schrempf%40kontron.de%7Ca88f0cdec137451033ab08d86934dbe6%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637375023034158708&amp;sdata=l2pnC0dfueaAGSfwHOK3OpBUJ%2FxnbFKrlpRWlBakVvo%3D&amp;reserved=0

> ---

>   drivers/gpu/drm/bridge/samsung-dsim.c | 9 ++++++---

>   1 file changed, 6 insertions(+), 3 deletions(-)

> 

> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c

> index fbd87a74eb9f..42b49546dd00 100644

> --- a/drivers/gpu/drm/bridge/samsung-dsim.c

> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c

> @@ -740,20 +740,23 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)

>   {

>   	struct drm_display_mode *m = &dsi->mode;

>   	unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;

> +	int bpp;

>   	u32 reg;

>   

>   	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {

> +		bpp = mipi_dsi_pixel_format_to_bpp(dsi->format) / 8;

> +

>   		reg = DSIM_CMD_ALLOW(0xf)

>   			| DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)

>   			| DSIM_MAIN_VBP(m->vtotal - m->vsync_end);

>   		samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);

>   

> -		reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)

> -			| DSIM_MAIN_HBP(m->htotal - m->hsync_end);

> +		reg = DSIM_MAIN_HFP((m->hsync_start - m->hdisplay) * bpp / dsi->lanes)

> +			| DSIM_MAIN_HBP((m->htotal - m->hsync_end) * bpp / dsi->lanes);

>   		samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);

>   

>   		reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)

> -			| DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);

> +			| DSIM_MAIN_HSA((m->hsync_end - m->hsync_start) * bpp / dsi->lanes);

>   		samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);


I did a bit of testing with the DSIM and BLK-CTL on i.MX8MM and I'm 
seeing some issues with these settings. I think your changes are 
correct, but to get my display configuration working I still need to add 
this [1] ported from the downstream driver [2]. Though, I can't really 
tell if this is a correct fix or something else is wrong.

[1] 
https://github.com/fschrempf/linux/commit/65e50ebc38706ca9b5b3dec8a6ab9b28907f5d3a
[2] 
https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n932

>   	}

>   	reg =  DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |

>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index fbd87a74eb9f..42b49546dd00 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -740,20 +740,23 @@  static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)
 {
 	struct drm_display_mode *m = &dsi->mode;
 	unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
+	int bpp;
 	u32 reg;
 
 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
+		bpp = mipi_dsi_pixel_format_to_bpp(dsi->format) / 8;
+
 		reg = DSIM_CMD_ALLOW(0xf)
 			| DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
 			| DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
 		samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);
 
-		reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
-			| DSIM_MAIN_HBP(m->htotal - m->hsync_end);
+		reg = DSIM_MAIN_HFP((m->hsync_start - m->hdisplay) * bpp / dsi->lanes)
+			| DSIM_MAIN_HBP((m->htotal - m->hsync_end) * bpp / dsi->lanes);
 		samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
 
 		reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
-			| DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
+			| DSIM_MAIN_HSA((m->hsync_end - m->hsync_start) * bpp / dsi->lanes);
 		samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
 	}
 	reg =  DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |