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[71.195.31.37]) by mx.google.com with ESMTPSA id s3sm4838465igr.14.2014.03.28.06.44.35 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 28 Mar 2014 06:44:36 -0700 (PDT) From: Alex Elder To: viresh.linux@gmail.com, shiraz.hashim@gmail.com Subject: [RFC PATCH] ARM: spear: send SGI to trigger secondary CPU start Date: Fri, 28 Mar 2014 08:44:57 -0500 Message-Id: <1396014297-31435-1-git-send-email-elder@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140328_094502_597159_2483767F X-CRM114-Status: GOOD ( 12.51 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.213.175 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: vk.vipin@gmail.com, spear-devel@list.st.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: elder@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The ARM spear machine uses the "holding pen" mechanism for starting secondary CPUs. Most implementations indicate it's a secondary core's time to start by writing its CPU id into a location and then signaling the core with a software-generated interrupt. The spear code does not send the signal. Comments elsewhere in the code seem to indicate it should: The BootMonitor waits until it receives a soft interrupt, and then the secondary CPU branches to this address. I suspect this is an oversight, and this patch proposes a remedy. *** I need the attention of a maintainer to verify this *** because I am unable to test this proposed change. Signed-off-by: Alex Elder --- arch/arm/mach-spear/platsmp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c index 5c4a198..c9064fe 100644 --- a/arch/arm/mach-spear/platsmp.c +++ b/arch/arm/mach-spear/platsmp.c @@ -62,6 +62,8 @@ static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle) flush_cache_all(); outer_flush_all(); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { smp_rmb();