diff mbox series

[PULL,24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs

Message ID 20200619062518.1718523-25-alistair.francis@wdc.com
State New
Headers show
Series [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register | expand

Commit Message

Alistair Francis June 19, 2020, 6:25 a.m. UTC 
From: Bin Meng <bin.meng@windriver.com>

At present the GPIO output IRQs are triggered each time any GPIO
register is written. However this is not correct. We should only
trigger the output IRQ when the pin is configured as output enable.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-9-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_gpio.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
index 0d0fd2ba5e..aac6b44cac 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/riscv/sifive_gpio.c
@@ -76,7 +76,9 @@  static void update_state(SIFIVEGPIOState *s)
             actual_value = pull;
         }
 
-        qemu_set_irq(s->output[i], actual_value);
+        if (output_en) {
+            qemu_set_irq(s->output[i], actual_value);
+        }
 
         /* Input value */
         ival = input_en && actual_value;