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[RFC,07/12] mmc: mmci: Qcomm: Add 3 clock cycle delay after each register write

Message ID 1398116909-31517-1-git-send-email-srinivas.kandagatla@linaro.org
State New
Headers show

Commit Message

Srinivas Kandagatla April 21, 2014, 9:48 p.m. UTC 
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

This patch adds a 3 clock cycle delay required after writing to controller
registers on Qualcomm SOCs. Without this delay cards are either not detected
or fails as soon as card is put into data transfer mode.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 drivers/mmc/host/mmci.c |    1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 86bf330..2dc7581 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -168,6 +168,7 @@  static struct variant_data variant_qcom = {
 	.fifosize		= 16 * 4,
 	.fifohalfsize		= 8 * 4,
 	.clkreg			= MCI_CLK_ENABLE,
+	.reg_write_delay	= 3,
 	.blksz_datactrl4	= true,
 	.datalength_bits	= 24,
 	.blksz_datactrl4	= true,