| Message ID | 1398274575-24818-1-git-send-email-rogerq@ti.com |
|---|---|
| State | New |
| Headers | show |
Tony, On 04/23/2014 08:36 PM, Roger Quadros wrote: > From: Balaji T K <balajitk@ti.com> > > Add nodes for OCP2SCP3 bus, SATA controller and SATA PHY. > > [Roger Q] Clean up. > > CC: Benoit Cousson <bcousson@baylibre.com> > Signed-off-by: Balaji T K <balajitk@ti.com> > Signed-off-by: Roger Quadros <rogerq@ti.com> > --- > arch/arm/boot/dts/dra7.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi > index 1c0f8e1..084f42e 100644 > --- a/arch/arm/boot/dts/dra7.dtsi > +++ b/arch/arm/boot/dts/dra7.dtsi > @@ -789,6 +789,45 @@ > dma-names = "tx0", "rx0"; > status = "disabled"; > }; > + > + omap_control_sata: control-phy@4a002374 { > + compatible = "ti,control-phy-pipe3"; > + reg = <0x4a002374 0x4>; > + reg-names = "power"; > + clocks = <&sys_clkin1>; > + clock-names = "sysclk"; > + }; > + > + /* OCP2SCP3 */ > + ocp2scp@4a090000 { > + compatible = "ti,omap-ocp2scp"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + reg = <0x4a090000 0x20>; > + ti,hwmods = "ocp2scp3"; > + sata_phy: phy@4A096000 { > + compatible = "ti,phy-pipe3-sata"; > + reg = <0x4A096000 0x80>, /* phy_rx */ > + <0x4A096400 0x64>, /* phy_tx */ > + <0x4A096800 0x40>; /* pll_ctrl */ > + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; > + ctrl-module = <&omap_control_sata>; > + clocks = <&sys_clkin1>; > + clock-names = "sysclk"; > + #phy-cells = <0>; > + }; > + }; > + > + sata: sata@4a141100 { > + compatible = "snps,dwc-ahci"; > + reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; > + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; This will need to be changed like so if the IRQ crossbar changes [1] go in + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; cheers, -roger [1] - http://article.gmane.org/gmane.linux.documentation/23293 > + phys = <&sata_phy>; > + phy-names = "sata-phy"; > + clocks = <&sata_ref_clk>; > + ti,hwmods = "sata"; > + }; > }; > }; > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
* Roger Quadros <rogerq@ti.com> [140507 01:15]: > Tony, > > On 04/23/2014 08:36 PM, Roger Quadros wrote: > > From: Balaji T K <balajitk@ti.com> > > > > Add nodes for OCP2SCP3 bus, SATA controller and SATA PHY. > > + sata: sata@4a141100 { > > + compatible = "snps,dwc-ahci"; > > + reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; > > + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; > > This will need to be changed like so if the IRQ crossbar changes [1] go in > > + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; > Adding this as is into omap-for-v3.16/dt thanks. Sounds like the crossbar needs more work. Tony -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1c0f8e1..084f42e 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -789,6 +789,45 @@ dma-names = "tx0", "rx0"; status = "disabled"; }; + + omap_control_sata: control-phy@4a002374 { + compatible = "ti,control-phy-pipe3"; + reg = <0x4a002374 0x4>; + reg-names = "power"; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + }; + + /* OCP2SCP3 */ + ocp2scp@4a090000 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x4a090000 0x20>; + ti,hwmods = "ocp2scp3"; + sata_phy: phy@4A096000 { + compatible = "ti,phy-pipe3-sata"; + reg = <0x4A096000 0x80>, /* phy_rx */ + <0x4A096400 0x64>, /* phy_tx */ + <0x4A096800 0x40>; /* pll_ctrl */ + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + ctrl-module = <&omap_control_sata>; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + #phy-cells = <0>; + }; + }; + + sata: sata@4a141100 { + compatible = "snps,dwc-ahci"; + reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + phys = <&sata_phy>; + phy-names = "sata-phy"; + clocks = <&sata_ref_clk>; + ti,hwmods = "sata"; + }; }; };