| Message ID | 20201015190332.1182588-1-dmitry.baryshkov@linaro.org |
|---|---|
| State | Accepted |
| Commit | 5047ab95bb7db0e7b2ecfd5e9bcafc7fd822c652 |
| Headers | show |
| Series | [1/4] drm/msm/dsi_pll_7nm: restore VCO rate during restore_state | expand |
Hello: This series was applied to qcom/linux.git (refs/heads/for-next): On Thu, 15 Oct 2020 22:03:29 +0300 you wrote: > PHY disable/enable resets PLL registers to default values. Thus in > addition to restoring several registers we also need to restore VCO rate > settings. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") > > [...] Here is the summary with links: - [1/4] drm/msm/dsi_pll_7nm: restore VCO rate during restore_state https://git.kernel.org/qcom/c/5047ab95bb7d - [2/4] drm/msm/dsi_pll_10nm: restore VCO rate during restore_state https://git.kernel.org/qcom/c/a4ccc37693a2 - [3/4] drm/msm/dsi_phy_7nm: implement PHY disabling https://git.kernel.org/qcom/c/b66ccc571319 - [4/4] drm/msm/dsi_phy_10nm: implement PHY disabling https://git.kernel.org/qcom/c/e92ce317fbeb You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c index de0dfb815125..93bf142e4a4e 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c @@ -585,6 +585,7 @@ static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll) struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; void __iomem *phy_base = pll_7nm->phy_cmn_mmio; u32 val; + int ret; val = pll_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); val &= ~0x3; @@ -599,6 +600,13 @@ static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll) val |= cached->pll_mux; pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); + ret = dsi_pll_7nm_vco_set_rate(&pll->clk_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate); + if (ret) { + DRM_DEV_ERROR(&pll_7nm->pdev->dev, + "restore vco rate failed. ret=%d\n", ret); + return ret; + } + DBG("DSI PLL%d", pll_7nm->id); return 0;
PHY disable/enable resets PLL registers to default values. Thus in addition to restoring several registers we also need to restore VCO rate settings. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 8 ++++++++ 1 file changed, 8 insertions(+)