| Message ID | 20200926130004.13528-7-kholk11@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | Implement firmware quirks for Qualcomm ARM-SMMUv2 | expand |
On 2020-09-26 14:00, kholk11@gmail.com wrote: > From: AngeloGioacchino Del Regno <kholk11@gmail.com> > > Move the stream mapping reset logic from arm_smmu_device_reset into > a separate arm_smmu_stream_mapping_reset function, in preparation > for implementing an implementation detail. > > This commit brings no functional changes. Please coordinate with Bjorn's series so you're not wasting time developing 'competing' implementations of the exact same thing. You don't need these last 3 patches, for reasons I've already explained over there. Robin. > Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> > --- > drivers/iommu/arm/arm-smmu/arm-smmu.c | 19 +++++++++++++------ > 1 file changed, 13 insertions(+), 6 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c > index 446a78dde9cd..8c070c493315 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c > @@ -1652,14 +1652,9 @@ static struct iommu_ops arm_smmu_ops = { > .pgsize_bitmap = -1UL, /* Restricted during device attach */ > }; > > -static void arm_smmu_device_reset(struct arm_smmu_device *smmu) > +static void arm_smmu_stream_mapping_reset(struct arm_smmu_device *smmu) > { > int i; > - u32 reg; > - > - /* clear global FSR */ > - reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); > - arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, reg); > > /* > * Reset stream mapping groups: Initial values mark all SMRn as > @@ -1673,6 +1668,18 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) > arm_smmu_write_context_bank(smmu, i); > arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); > } > +} > + > +static void arm_smmu_device_reset(struct arm_smmu_device *smmu) > +{ > + u32 reg; > + > + /* clear global FSR */ > + reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); > + arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, reg); > + > + /* Reset stream mapping */ > + arm_smmu_stream_mapping_reset(smmu); > > /* Invalidate the TLB, just in case */ > arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLH, QCOM_DUMMY_VAL); >
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 446a78dde9cd..8c070c493315 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1652,14 +1652,9 @@ static struct iommu_ops arm_smmu_ops = { .pgsize_bitmap = -1UL, /* Restricted during device attach */ }; -static void arm_smmu_device_reset(struct arm_smmu_device *smmu) +static void arm_smmu_stream_mapping_reset(struct arm_smmu_device *smmu) { int i; - u32 reg; - - /* clear global FSR */ - reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); - arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, reg); /* * Reset stream mapping groups: Initial values mark all SMRn as @@ -1673,6 +1668,18 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) arm_smmu_write_context_bank(smmu, i); arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); } +} + +static void arm_smmu_device_reset(struct arm_smmu_device *smmu) +{ + u32 reg; + + /* clear global FSR */ + reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); + arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, reg); + + /* Reset stream mapping */ + arm_smmu_stream_mapping_reset(smmu); /* Invalidate the TLB, just in case */ arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLH, QCOM_DUMMY_VAL);