| Message ID | 1398759614-13217-1-git-send-email-srinivas.kandagatla@linaro.org |
|---|---|
| State | New |
| Headers | show |
On Tue, Apr 29, 2014 at 10:20 AM, <srinivas.kandagatla@linaro.org> wrote: > From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > > Most of the Qcomm SD card controller registers must be updated to the MCLK > domain so subsequent writes to registers will be ignored until 3 clock cycles > have passed. > > This patch adds a 3 clock cycle delay required after writing to controller > registers on Qualcomm SOCs. Without this delay all the register writes are not > successfull, resulting in not detecting cards. > > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Sounds like someone decided to clock the internal state machine in the MMCI using MCLK instead of PCLK :-( A bit nasty if this ends up in the fastpath (irq) though. Which it invariably does, right? > + /* > + * On QCom SD card controller, registers must be updated to the > + * MCLK domain so subsequent writes to this register will be ignored > + * for 3 clk cycles. > + */ > + if (host->hw_designer == AMBA_VENDOR_QCOM) > + udelay(1 + ((3 * USEC_PER_SEC)/host->mclk)); Add a new field in vendor data instead, and use DIV_ROUND_UP(): static struct variant_data variant_qcom = { .mclk_delayed_writes = true, (...) if (host->vendor->mclk_delayed_writes) udelay(DIV_ROUND_UP((3 * USEC_PER_SEC), host->mclk)); You get the idea. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Thanks Linus W for reviewing the patches. On 13/05/14 08:29, Linus Walleij wrote: > On Tue, Apr 29, 2014 at 10:20 AM, <srinivas.kandagatla@linaro.org> wrote: > >> From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> >> >> Most of the Qcomm SD card controller registers must be updated to the MCLK >> domain so subsequent writes to registers will be ignored until 3 clock cycles >> have passed. >> >> This patch adds a 3 clock cycle delay required after writing to controller >> registers on Qualcomm SOCs. Without this delay all the register writes are not >> successfull, resulting in not detecting cards. >> >> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > > Sounds like someone decided to clock the internal state machine > in the MMCI using MCLK instead of PCLK :-( > > A bit nasty if this ends up in the fastpath (irq) though. Which it > invariably does, right? yes, Its going to for Qcom SOC. > >> + /* >> + * On QCom SD card controller, registers must be updated to the >> + * MCLK domain so subsequent writes to this register will be ignored >> + * for 3 clk cycles. >> + */ >> + if (host->hw_designer == AMBA_VENDOR_QCOM) >> + udelay(1 + ((3 * USEC_PER_SEC)/host->mclk)); > > Add a new field in vendor data instead, and use DIV_ROUND_UP(): > yes, that makes sense.. > static struct variant_data variant_qcom = { > .mclk_delayed_writes = true, > (...) > > if (host->vendor->mclk_delayed_writes) > udelay(DIV_ROUND_UP((3 * USEC_PER_SEC), host->mclk)); > > You get the idea. > Got it. > Yours, > Linus Walleij > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 4f8d0ba..f73dc48 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -179,6 +179,14 @@ static inline u32 mmci_readl(struct mmci_host *host, u32 off) static inline void mmci_writel(struct mmci_host *host, u32 data, u32 off) { writel(data, host->base + off); + + /* + * On QCom SD card controller, registers must be updated to the + * MCLK domain so subsequent writes to this register will be ignored + * for 3 clk cycles. + */ + if (host->hw_designer == AMBA_VENDOR_QCOM) + udelay(1 + ((3 * USEC_PER_SEC)/host->mclk)); } static int mmci_card_busy(struct mmc_host *mmc)