diff mbox series

ARM: dts: dra7: add second SHA instance

Message ID 20200907095246.1651-1-t-kristo@ti.com
State New
Headers show
Series ARM: dts: dra7: add second SHA instance | expand

Commit Message

Tero Kristo Sept. 7, 2020, 9:52 a.m. UTC 
DRA7 SoC has two SHA instances, add the missing second one under the
main dts file.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
Hi Tony,

This patch depends on: https://patchwork.kernel.org/patch/11760193/

 arch/arm/boot/dts/dra7.dtsi | 34 ++++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

Comments

Tony Lindgren Nov. 16, 2020, 11:31 a.m. UTC | #1 
* Tero Kristo <t-kristo@ti.com> [200907 12:52]:
> DRA7 SoC has two SHA instances, add the missing second one under the

> main dts file.

> 

> Signed-off-by: Tero Kristo <t-kristo@ti.com>

> ---

> Hi Tony,

> 

> This patch depends on: https://patchwork.kernel.org/patch/11760193/


Applying this into omap-for-v5.11/dt thanks.

Tony
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index cca6b123856f..b9cd5bacd606 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -932,7 +932,7 @@ 
 			};
 		};
 
-		sham_target: target-module@4b101000 {
+		sham1_target: target-module@4b101000 {
 			compatible = "ti,sysc-omap3-sham", "ti,sysc";
 			reg = <0x4b101100 0x4>,
 			      <0x4b101110 0x4>,
@@ -951,7 +951,7 @@ 
 			#size-cells = <1>;
 			ranges = <0x0 0x4b101000 0x1000>;
 
-			sham: sham@0 {
+			sham1: sham@0 {
 				compatible = "ti,omap5-sham";
 				reg = <0 0x300>;
 				interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
@@ -962,6 +962,36 @@ 
 			};
 		};
 
+		sham2_target: target-module@42701000 {
+			compatible = "ti,sysc-omap3-sham", "ti,sysc";
+			reg = <0x42701100 0x4>,
+			      <0x42701110 0x4>,
+			      <0x42701114 0x4>;
+			reg-names = "rev", "sysc", "syss";
+			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+					 SYSC_OMAP2_AUTOIDLE)>;
+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+					<SYSC_IDLE_NO>,
+					<SYSC_IDLE_SMART>;
+			ti,syss-mask = <1>;
+			/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+			clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>;
+			clock-names = "fck";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x42701000 0x1000>;
+
+			sham2: sham@0 {
+				compatible = "ti,omap5-sham";
+				reg = <0 0x300>;
+				interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&edma_xbar 165 0>;
+				dma-names = "rx";
+				clocks = <&l3_iclk_div>;
+				clock-names = "fck";
+			};
+		};
+
 		opp_supply_mpu: opp-supply@4a003b20 {
 			compatible = "ti,omap5-opp-supply";
 			reg = <0x4a003b20 0xc>;