@@ -1117,11 +1117,11 @@ static void create_pcie_irq_map(const VirtMachineState *vms,
int first_irq, const char *nodename)
{
int devfn, pin;
- uint32_t full_irq_map[4 * 4 * 10] = { 0 };
+ uint32_t full_irq_map[4 * PCI_NUM_PINS * 10] = { 0 };
uint32_t *irq_map = full_irq_map;
for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
- for (pin = 0; pin < 4; pin++) {
+ for (pin = 0; pin < PCI_NUM_PINS; pin++) {
int irq_type = GIC_FDT_IRQ_TYPE_SPI;
int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
@@ -1018,7 +1018,7 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
if (pic_irq < 16) {
/* The pic level is the logical OR of all the PCI irqs mapped to it. */
pic_level = 0;
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < PCI_NUM_PINS; i++) {
if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
pic_level |= pci_irq_levels[i];
}
@@ -75,7 +75,7 @@ enum {
struct PCIVPBState {
PCIHostState parent_obj;
- qemu_irq irq[4];
+ qemu_irq irq[PCI_NUM_PINS];
MemoryRegion controlregs;
MemoryRegion mem_config;
MemoryRegion mem_config2;
@@ -412,7 +412,7 @@ static void pci_vpb_realize(DeviceState *dev, Error **errp)
object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_VERSATILE_PCI_HOST);
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < PCI_NUM_PINS; i++) {
sysbus_init_irq(sbd, &s->irq[i]);
}
@@ -422,7 +422,7 @@ static void pci_vpb_realize(DeviceState *dev, Error **errp)
mapfn = pci_vpb_map_irq;
}
- pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, 4);
+ pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, PCI_NUM_PINS);
/* Our memory regions are:
* 0 : our control registers
Use self-explicit PCI_NUM_PINS definition instead of magic value. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- hw/arm/virt.c | 4 ++-- hw/mips/gt64xxx_pci.c | 2 +- hw/pci-host/versatile.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-)