| Message ID | 1400849527-7384-1-git-send-email-srinivas.kandagatla@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 23 May 2014 14:52, <srinivas.kandagatla@linaro.org> wrote: > From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > > This patch adds 8bit bus enable to variant structure giving more flexibility > to the driver to support more SOCs which have different clock register layout. > > Without this patch other new SOCs like Qcom will have to add more code > to special case them. > > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> > --- > drivers/mmc/host/mmci.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c > index dec70d2..a81f303 100644 > --- a/drivers/mmc/host/mmci.c > +++ b/drivers/mmc/host/mmci.c > @@ -52,6 +52,7 @@ static unsigned int fmax = 515633; > * struct variant_data - MMCI variant-specific quirks > * @clkreg: default value for MCICLOCK register > * @clkreg_enable: enable value for MMCICLOCK register > + * @clkreg_8bit_bus_enable: enable value for 8 bit bus > * @datalength_bits: number of bits in the MMCIDATALENGTH register > * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY > * is asserted (likewise for RX) > @@ -74,6 +75,7 @@ static unsigned int fmax = 515633; > struct variant_data { > unsigned int clkreg; > unsigned int clkreg_enable; > + unsigned int clkreg_8bit_bus_enable; > unsigned int datalength_bits; > unsigned int fifosize; > unsigned int fifohalfsize; > @@ -116,6 +118,7 @@ static struct variant_data variant_u300 = { > .fifosize = 16 * 4, > .fifohalfsize = 8 * 4, > .clkreg_enable = MCI_ST_U300_HWFCEN, > + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, Linus, will have to confirm this. I don't know if the u300 variant support 8-bit. Kind regards Ulf Hansson > .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, > .datalength_bits = 16, > .sdio = true, > @@ -144,6 +147,7 @@ static struct variant_data variant_ux500 = { > .fifohalfsize = 8 * 4, > .clkreg = MCI_CLK_ENABLE, > .clkreg_enable = MCI_ST_UX500_HWFCEN, > + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, > .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, > .datalength_bits = 24, > .sdio = true, > @@ -160,6 +164,7 @@ static struct variant_data variant_ux500v2 = { > .fifohalfsize = 8 * 4, > .clkreg = MCI_CLK_ENABLE, > .clkreg_enable = MCI_ST_UX500_HWFCEN, > + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, > .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, > .datalength_bits = 24, > .sdio = true, > @@ -340,7 +345,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) > if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) > clk |= MCI_4BIT_BUS; > if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) > - clk |= MCI_ST_8BIT_BUS; > + clk |= variant->clkreg_8bit_bus_enable; > > if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) > clk |= MCI_ST_UX500_NEG_EDGE; > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Hi Linus W, On 26/05/14 11:07, Ulf Hansson wrote: >> unsigned int fifosize; >> > unsigned int fifohalfsize; >> >@@ -116,6 +118,7 @@ static struct variant_data variant_u300 = { >> > .fifosize = 16 * 4, >> > .fifohalfsize = 8 * 4, >> > .clkreg_enable = MCI_ST_U300_HWFCEN, >> >+ .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, > Linus, will have to confirm this. I don't know if the u300 variant > support 8-bit. > Do you know if u300 supports 8BIT bus? thanks, srini > Kind regards > Ulf Hansson > -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, May 28, 2014 at 9:27 AM, Srinivas Kandagatla <srinivas.kandagatla@linaro.org> wrote: > Hi Linus W, > On 26/05/14 11:07, Ulf Hansson wrote: >>> >>> unsigned int fifosize; >>> > unsigned int fifohalfsize; >>> >@@ -116,6 +118,7 @@ static struct variant_data variant_u300 = { >>> > .fifosize = 16 * 4, >>> > .fifohalfsize = 8 * 4, >>> > .clkreg_enable = MCI_ST_U300_HWFCEN, >>> >+ .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, >> >> Linus, will have to confirm this. I don't know if the u300 variant >> support 8-bit. >> > > Do you know if u300 supports 8BIT bus? Yes it does actually. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index dec70d2..a81f303 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -52,6 +52,7 @@ static unsigned int fmax = 515633; * struct variant_data - MMCI variant-specific quirks * @clkreg: default value for MCICLOCK register * @clkreg_enable: enable value for MMCICLOCK register + * @clkreg_8bit_bus_enable: enable value for 8 bit bus * @datalength_bits: number of bits in the MMCIDATALENGTH register * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY * is asserted (likewise for RX) @@ -74,6 +75,7 @@ static unsigned int fmax = 515633; struct variant_data { unsigned int clkreg; unsigned int clkreg_enable; + unsigned int clkreg_8bit_bus_enable; unsigned int datalength_bits; unsigned int fifosize; unsigned int fifohalfsize; @@ -116,6 +118,7 @@ static struct variant_data variant_u300 = { .fifosize = 16 * 4, .fifohalfsize = 8 * 4, .clkreg_enable = MCI_ST_U300_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 16, .sdio = true, @@ -144,6 +147,7 @@ static struct variant_data variant_ux500 = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 24, .sdio = true, @@ -160,6 +164,7 @@ static struct variant_data variant_ux500v2 = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 24, .sdio = true, @@ -340,7 +345,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) clk |= MCI_4BIT_BUS; if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) - clk |= MCI_ST_8BIT_BUS; + clk |= variant->clkreg_8bit_bus_enable; if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) clk |= MCI_ST_UX500_NEG_EDGE;