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[RFC,v3,9/9] arm64: dts: lx2160a: fix FlexSPI clock

Message ID 20201108185113.31377-10-michael@walle.cc
State New
Headers show
Series clk: qoriq fixes and new fsl-flexspi driver | expand

Commit Message

Michael Walle Nov. 8, 2020, 6:51 p.m. UTC
Now that we have a proper driver for the FlexSPI interface use it. This
will fix SCK frequency switching on Layerscape SoCs.

Signed-off-by: Michael Walle <michael@walle.cc>
---
Thanks to Vladimir Oltean, this was partially tested on a LX2160A RDB. But
this patch is marked as RFC nonetheless, because there is too much
difference in the clock tree between LS1028A and LX2160A. It would be nice
if someone could test it and add a Tested-by.

Changes since v2:
 - none

Changes since v1:
 - none

 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)
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Patch

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 0a54a54ec770..130de5f7ff5e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -661,9 +661,20 @@ 
 		};
 
 		dcfg: syscon@1e00000 {
-			compatible = "fsl,lx2160a-dcfg", "syscon";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,lx2160a-dcfg", "syscon", "simple-mfd";
 			reg = <0x0 0x1e00000 0x0 0x10000>;
+			ranges = <0x0 0x0 0x1e00000 0x10000>;
 			little-endian;
+
+			fspi_clk: clock-controller@900 {
+				compatible = "fsl,lx2160a-flexspi-clk";
+				reg = <0x900 0x4>;
+				#clock-cells = <0>;
+				clocks = <&clockgen 4 0>;
+				clock-output-names = "fspi_clk";
+			};
 		};
 
 		tmu: tmu@1f80000 {
@@ -778,7 +789,7 @@ 
 			      <0x0 0x20000000 0x0 0x10000000>;
 			reg-names = "fspi_base", "fspi_mmap";
 			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+			clocks = <&clockgen 4 3>, <&fspi_clk>;
 			clock-names = "fspi_en", "fspi";
 			status = "disabled";
 		};