| Message ID | 20201105231912.69527-2-coiby.xu@gmail.com |
|---|---|
| State | Accepted |
| Commit | 06abe8291bc31839950f7d0362d9979edc88a666 |
| Headers | show |
| Series | pinctrl: amd: debounce filter fixes | expand |
Hi, On 11/6/20 12:19 AM, Coiby Xu wrote: > The correct way to disable debounce filter is to clear bit 5 and 6 > of the register. > > Cc: Hans de Goede <hdegoede@redhat.com> > Link: https://lore.kernel.org/linux-gpio/df2c008b-e7b5-4fdd-42ea-4d1c62b52139@redhat.com/ > Signed-off-by: Coiby Xu <coiby.xu@gmail.com> Thanks, patch looks good to me: Reviewed-by: Hans de Goede <hdegoede@redhat.com> Regards, Hans > --- > drivers/pinctrl/pinctrl-amd.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c > index 9a760f5cd7ed..d6b2b4bd337c 100644 > --- a/drivers/pinctrl/pinctrl-amd.c > +++ b/drivers/pinctrl/pinctrl-amd.c > @@ -166,14 +166,14 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, > pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); > pin_reg |= BIT(DB_TMR_LARGE_OFF); > } else { > - pin_reg &= ~DB_CNTRl_MASK; > + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); > ret = -EINVAL; > } > } else { > pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); > pin_reg &= ~BIT(DB_TMR_LARGE_OFF); > pin_reg &= ~DB_TMR_OUT_MASK; > - pin_reg &= ~DB_CNTRl_MASK; > + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); > } > writel(pin_reg, gpio_dev->base + offset * 4); > raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); >
On Fri, Nov 6, 2020 at 12:19 AM Coiby Xu <coiby.xu@gmail.com> wrote: > The correct way to disable debounce filter is to clear bit 5 and 6 > of the register. > > Cc: Hans de Goede <hdegoede@redhat.com> > Link: https://lore.kernel.org/linux-gpio/df2c008b-e7b5-4fdd-42ea-4d1c62b52139@redhat.com/ > Signed-off-by: Coiby Xu <coiby.xu@gmail.com> This patch applied for fixes and tagged for stable. Yours, Linus Walleij
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 9a760f5cd7ed..d6b2b4bd337c 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -166,14 +166,14 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); pin_reg |= BIT(DB_TMR_LARGE_OFF); } else { - pin_reg &= ~DB_CNTRl_MASK; + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); ret = -EINVAL; } } else { pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); pin_reg &= ~BIT(DB_TMR_LARGE_OFF); pin_reg &= ~DB_TMR_OUT_MASK; - pin_reg &= ~DB_CNTRl_MASK; + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); } writel(pin_reg, gpio_dev->base + offset * 4); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
The correct way to disable debounce filter is to clear bit 5 and 6 of the register. Cc: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/linux-gpio/df2c008b-e7b5-4fdd-42ea-4d1c62b52139@redhat.com/ Signed-off-by: Coiby Xu <coiby.xu@gmail.com> --- drivers/pinctrl/pinctrl-amd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)