| Message ID | 20201118135822.9582-4-jbx6244@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v5,1/7] clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks | expand |
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml index 4110d003c..585a8d3b9 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml @@ -42,6 +42,9 @@ properties: description: This soc uses GRF regs to switch the HDMI TX input between vop0 and vop1. + "#sound-dai-cells": + const: 0 + ports: type: object @@ -101,6 +104,7 @@ examples: pinctrl-names = "default"; power-domains = <&power RK3066_PD_VIO>; rockchip,grf = <&grf>; + #sound-dai-cells = <0>; ports { #address-cells = <1>;
'#sound-dai-cells' is required to properly interpret the list of DAI specified in the 'sound-dai' property. Add it to rockchip,rk3066-hdmi.yaml to document that the rk3066 HDMI TX also can be used to transmit some audio. Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- .../devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml | 4 ++++ 1 file changed, 4 insertions(+)