@@ -201,7 +201,7 @@ void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf)
if (!list_empty(&cap->pending_buf_q)) {
v_buf = fimc_pending_queue_pop(cap);
- fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
+ fimc_hw_set_output_addr(fimc, &v_buf->addr, cap->buf_index);
v_buf->index = cap->buf_index;
/* Move the buffer to the capture active queue */
@@ -410,7 +410,7 @@ static void buffer_queue(struct vb2_buffer *vb)
int min_bufs;
spin_lock_irqsave(&fimc->slock, flags);
- fimc_prepare_addr(ctx, &buf->vb.vb2_buf, &ctx->d_frame, &buf->paddr);
+ fimc_prepare_addr(ctx, &buf->vb.vb2_buf, &ctx->d_frame, &buf->addr);
if (!test_bit(ST_CAPT_SUSPENDED, &fimc->state) &&
!test_bit(ST_CAPT_STREAM, &fimc->state) &&
@@ -419,7 +419,7 @@ static void buffer_queue(struct vb2_buffer *vb)
int buf_id = (vid_cap->reqbufs_count == 1) ? -1 :
vid_cap->buf_index;
- fimc_hw_set_output_addr(fimc, &buf->paddr, buf_id);
+ fimc_hw_set_output_addr(fimc, &buf->addr, buf_id);
buf->index = vid_cap->buf_index;
fimc_active_queue_add(vid_cap, buf);
@@ -325,7 +325,7 @@ static irqreturn_t fimc_irq_handler(int irq, void *priv)
/* The color format (colplanes, memplanes) must be already configured. */
int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
- struct fimc_frame *frame, struct fimc_addr *paddr)
+ struct fimc_frame *frame, struct fimc_addr *addr)
{
int ret = 0;
u32 pix_size;
@@ -338,42 +338,40 @@ int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
dbg("memplanes= %d, colplanes= %d, pix_size= %d",
frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
- paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
+ addr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
if (frame->fmt->memplanes == 1) {
switch (frame->fmt->colplanes) {
case 1:
- paddr->cb = 0;
- paddr->cr = 0;
+ addr->cb = 0;
+ addr->cr = 0;
break;
case 2:
/* decompose Y into Y/Cb */
- paddr->cb = (u32)(paddr->y + pix_size);
- paddr->cr = 0;
+ addr->cb = (u32)(addr->y + pix_size);
+ addr->cr = 0;
break;
case 3:
- paddr->cb = (u32)(paddr->y + pix_size);
+ addr->cb = (u32)(addr->y + pix_size);
/* decompose Y into Y/Cb/Cr */
if (FIMC_FMT_YCBCR420 == frame->fmt->color)
- paddr->cr = (u32)(paddr->cb
- + (pix_size >> 2));
+ addr->cr = (u32)(addr->cb + (pix_size >> 2));
else /* 422 */
- paddr->cr = (u32)(paddr->cb
- + (pix_size >> 1));
+ addr->cr = (u32)(addr->cb + (pix_size >> 1));
break;
default:
return -EINVAL;
}
} else if (!frame->fmt->mdataplanes) {
if (frame->fmt->memplanes >= 2)
- paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
+ addr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
if (frame->fmt->memplanes == 3)
- paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
+ addr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
}
- dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
- paddr->y, paddr->cb, paddr->cr, ret);
+ dbg("DMA ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
+ addr->y, addr->cb, addr->cr, ret);
return ret;
}
@@ -202,10 +202,10 @@ struct fimc_scaler {
};
/**
- * struct fimc_addr - the FIMC physical address set for DMA
- * @y: luminance plane physical address
- * @cb: Cb plane physical address
- * @cr: Cr plane physical address
+ * struct fimc_addr - the FIMC address set for DMA
+ * @y: luminance plane address
+ * @cb: Cb plane address
+ * @cr: Cr plane address
*/
struct fimc_addr {
u32 y;
@@ -217,13 +217,13 @@ struct fimc_addr {
* struct fimc_vid_buffer - the driver's video buffer
* @vb: v4l videobuf buffer
* @list: linked list structure for buffer queue
- * @paddr: precalculated physical address set
+ * @addr: precalculated DMA address set
* @index: buffer index for the output DMA engine
*/
struct fimc_vid_buffer {
struct vb2_v4l2_buffer vb;
struct list_head list;
- struct fimc_addr paddr;
+ struct fimc_addr addr;
int index;
};
@@ -239,7 +239,7 @@ struct fimc_vid_buffer {
* @height: image pixel weight
* @payload: image size in bytes (w x h x bpp)
* @bytesperline: bytesperline value for each plane
- * @paddr: image frame buffer physical addresses
+ * @addr: image frame buffer DMA addresses
* @dma_offset: DMA offset in bytes
* @fmt: fimc color format pointer
*/
@@ -254,7 +254,7 @@ struct fimc_frame {
u32 height;
unsigned int payload[VIDEO_MAX_PLANES];
unsigned int bytesperline[VIDEO_MAX_PLANES];
- struct fimc_addr paddr;
+ struct fimc_addr addr;
struct fimc_dma_offset dma_offset;
struct fimc_fmt *fmt;
u8 alpha;
@@ -626,7 +626,7 @@ int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
int fimc_set_scaler_info(struct fimc_ctx *ctx);
int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
- struct fimc_frame *frame, struct fimc_addr *paddr);
+ struct fimc_frame *frame, struct fimc_addr *addr);
void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);
void fimc_set_yuv_order(struct fimc_ctx *ctx);
void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf);
@@ -269,7 +269,7 @@ int fimc_is_cpu_set_power(struct fimc_is *is, int on)
mcuctl_write(0, is, REG_WDT_ISP);
/* Cortex-A5 start address setting */
- mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR);
+ mcuctl_write(is->memory.addr, is, MCUCTL_REG_BBOAR);
/* Enable and start Cortex-A5 */
pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
@@ -336,26 +336,26 @@ static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
struct device *dev = &is->pdev->dev;
is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
- &is->memory.paddr, GFP_KERNEL);
+ &is->memory.addr, GFP_KERNEL);
if (is->memory.vaddr == NULL)
return -ENOMEM;
is->memory.size = FIMC_IS_CPU_MEM_SIZE;
- dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr);
+ dev_info(dev, "FIMC-IS CPU memory base: %pad\n", &is->memory.addr);
- if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) {
+ if (((u32)is->memory.addr) & FIMC_IS_FW_ADDR_MASK) {
dev_err(dev, "invalid firmware memory alignment: %#x\n",
- (u32)is->memory.paddr);
+ (u32)is->memory.addr);
dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
- is->memory.paddr);
+ is->memory.addr);
return -EIO;
}
is->is_p_region = (struct is_region *)(is->memory.vaddr +
FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
- is->is_dma_p_region = is->memory.paddr +
+ is->is_dma_p_region = is->memory.addr +
FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
@@ -371,7 +371,7 @@ static void fimc_is_free_cpu_memory(struct fimc_is *is)
return;
dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
- is->memory.paddr);
+ is->memory.addr);
}
static void fimc_is_load_firmware(const struct firmware *fw, void *context)
@@ -416,7 +416,7 @@ static void fimc_is_load_firmware(const struct firmware *fw, void *context)
dev_info(dev, "loaded firmware: %s, rev. %s\n",
is->fw.info, is->fw.version);
- dev_dbg(dev, "FW size: %zu, paddr: %pad\n", fw->size, &is->memory.paddr);
+ dev_dbg(dev, "FW size: %zu, DMA addr: %pad\n", fw->size, &is->memory.addr);
is->is_shared_region->chip_id = 0xe4412;
is->is_shared_region->chip_rev_no = 1;
@@ -699,7 +699,7 @@ int fimc_is_hw_initialize(struct fimc_is *is)
}
pr_debug("shared region: %pad, parameter region: %pad\n",
- &is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET,
+ &is->memory.addr + FIMC_IS_SHARED_REGION_OFFSET,
&is->is_dma_p_region);
is->setfile.sub_index = 0;
@@ -174,7 +174,7 @@ struct is_af_info {
struct fimc_is_firmware {
const struct firmware *f_w;
- dma_addr_t paddr;
+ dma_addr_t addr;
void *vaddr;
unsigned int size;
@@ -185,8 +185,8 @@ struct fimc_is_firmware {
};
struct fimc_is_memory {
- /* physical base address */
- dma_addr_t paddr;
+ /* DMA base address */
+ dma_addr_t addr;
/* virtual base address */
void *vaddr;
/* total length */
@@ -272,9 +272,9 @@ void flite_hw_set_dma_buffer(struct fimc_lite *dev, struct flite_buffer *buf)
index = buf->index;
if (index == 0)
- writel(buf->paddr, dev->regs + FLITE_REG_CIOSA);
+ writel(buf->addr, dev->regs + FLITE_REG_CIOSA);
else
- writel(buf->paddr, dev->regs + FLITE_REG_CIOSAN(index - 1));
+ writel(buf->addr, dev->regs + FLITE_REG_CIOSAN(index - 1));
cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);
cfg |= BIT(index);
@@ -409,7 +409,7 @@ static void buffer_queue(struct vb2_buffer *vb)
unsigned long flags;
spin_lock_irqsave(&fimc->slock, flags);
- buf->paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
+ buf->addr = vb2_dma_contig_plane_dma_addr(vb, 0);
buf->index = fimc->buf_index++;
if (fimc->buf_index >= fimc->reqbufs_count)
@@ -93,13 +93,13 @@ struct flite_frame {
* struct flite_buffer - video buffer structure
* @vb: vb2 buffer
* @list: list head for the buffers queue
- * @paddr: DMA buffer start address
+ * @addr: DMA buffer start address
* @index: DMA start address register's index
*/
struct flite_buffer {
struct vb2_v4l2_buffer vb;
struct list_head list;
- dma_addr_t paddr;
+ dma_addr_t addr;
unsigned short index;
};
@@ -115,12 +115,12 @@ static void fimc_device_run(void *priv)
}
src_vb = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
- ret = fimc_prepare_addr(ctx, &src_vb->vb2_buf, sf, &sf->paddr);
+ ret = fimc_prepare_addr(ctx, &src_vb->vb2_buf, sf, &sf->addr);
if (ret)
goto dma_unlock;
dst_vb = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
- ret = fimc_prepare_addr(ctx, &dst_vb->vb2_buf, df, &df->paddr);
+ ret = fimc_prepare_addr(ctx, &dst_vb->vb2_buf, df, &df->addr);
if (ret)
goto dma_unlock;
@@ -152,8 +152,8 @@ static void fimc_device_run(void *priv)
fimc_hw_set_rgb_alpha(ctx);
fimc_hw_set_output_path(ctx);
}
- fimc_hw_set_input_addr(fimc, &sf->paddr);
- fimc_hw_set_output_addr(fimc, &df->paddr, -1);
+ fimc_hw_set_input_addr(fimc, &sf->addr);
+ fimc_hw_set_output_addr(fimc, &df->addr, -1);
fimc_activate_capture(ctx);
ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP);
@@ -526,30 +526,30 @@ void fimc_hw_set_output_path(struct fimc_ctx *ctx)
writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
}
-void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
+void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *addr)
{
u32 cfg = readl(dev->regs + FIMC_REG_CIREAL_ISIZE);
cfg |= FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
- writel(paddr->y, dev->regs + FIMC_REG_CIIYSA(0));
- writel(paddr->cb, dev->regs + FIMC_REG_CIICBSA(0));
- writel(paddr->cr, dev->regs + FIMC_REG_CIICRSA(0));
+ writel(addr->y, dev->regs + FIMC_REG_CIIYSA(0));
+ writel(addr->cb, dev->regs + FIMC_REG_CIICBSA(0));
+ writel(addr->cr, dev->regs + FIMC_REG_CIICRSA(0));
cfg &= ~FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
}
void fimc_hw_set_output_addr(struct fimc_dev *dev,
- struct fimc_addr *paddr, int index)
+ struct fimc_addr *addr, int index)
{
int i = (index == -1) ? 0 : index;
do {
- writel(paddr->y, dev->regs + FIMC_REG_CIOYSA(i));
- writel(paddr->cb, dev->regs + FIMC_REG_CIOCBSA(i));
- writel(paddr->cr, dev->regs + FIMC_REG_CIOCRSA(i));
+ writel(addr->y, dev->regs + FIMC_REG_CIOYSA(i));
+ writel(addr->cb, dev->regs + FIMC_REG_CIOCBSA(i));
+ writel(addr->cr, dev->regs + FIMC_REG_CIOCRSA(i));
dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
- i, paddr->y, paddr->cb, paddr->cr);
+ i, addr->y, addr->cb, addr->cr);
} while (index == -1 && ++i < FIMC_MAX_OUT_BUFS);
}
@@ -302,8 +302,8 @@ void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx);
void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
void fimc_hw_set_input_path(struct fimc_ctx *ctx);
void fimc_hw_set_output_path(struct fimc_ctx *ctx);
-void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
-void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
+void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *addr);
+void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *addr,
int index);
int fimc_hw_set_camera_source(struct fimc_dev *fimc,
struct fimc_source_info *cam);
This driver always operates on the DMA/IOVA addresses, so calling them physicall addresses is misleading, although when no IOMMU is used they equal each other. Fix this by renaming all such entries to 'addr' and adjusting comments. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> --- This patch was previously sent as part of "[PATCH 0/8] IOMMU-DMA - support old allocation algorithm used on ARM" patchset: https://lore.kernel.org/linux-samsung-soc/20200925141218.13550-1-m.szyprowski@samsung.com/ The IOMMU related changes are still under review, but this change is unrelated and it makes sense to aplly it separately. --- .../media/platform/exynos4-is/fimc-capture.c | 6 ++-- drivers/media/platform/exynos4-is/fimc-core.c | 28 +++++++++---------- drivers/media/platform/exynos4-is/fimc-core.h | 18 ++++++------ drivers/media/platform/exynos4-is/fimc-is.c | 20 ++++++------- drivers/media/platform/exynos4-is/fimc-is.h | 6 ++-- .../media/platform/exynos4-is/fimc-lite-reg.c | 4 +-- drivers/media/platform/exynos4-is/fimc-lite.c | 2 +- drivers/media/platform/exynos4-is/fimc-lite.h | 4 +-- drivers/media/platform/exynos4-is/fimc-m2m.c | 8 +++--- drivers/media/platform/exynos4-is/fimc-reg.c | 18 ++++++------ drivers/media/platform/exynos4-is/fimc-reg.h | 4 +-- 11 files changed, 58 insertions(+), 60 deletions(-)