| Message ID | 1606896236-62780-2-git-send-email-yash.shah@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | arch: riscv: add board and SoC DT file support | expand |
> -----Original Message----- > From: Andrew Lunn <andrew@lunn.ch> > Sent: 02 December 2020 20:28 > To: Yash Shah <yash.shah@openfive.com> > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux- > kernel@vger.kernel.org; linux-riscv@lists.infradead.org; > devicetree@vger.kernel.org; linux-gpio@vger.kernel.org; > broonie@kernel.org; gregkh@linuxfoundation.org; aou@eecs.berkeley.edu; > lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; > thierry.reding@gmail.com; peter@korsgaard.com; Paul Walmsley ( Sifive) > <paul.walmsley@sifive.com>; palmer@dabbelt.com; robh+dt@kernel.org; > bgolaszewski@baylibre.com; linus.walleij@linaro.org; Sachin Ghadi > <sachin.ghadi@openfive.com> > Subject: Re: [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to > support SiFive FU740 SoC > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > > diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt > > b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt > > index 6b25a80..1966b2c 100644 > > --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt > > +++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt > > @@ -3,9 +3,11 @@ Device tree configuration for i2c-ocores Required > > properties: > > - compatible : "opencores,i2c-ocores" > > "aeroflexgaisler,i2cmst" > > - "sifive,fu540-c000-i2c", "sifive,i2c0" > > + "sifive,<chip>-i2c", "sifive,i2c0" > > Please make this a full list. At some point, this file will get turned into yaml, at > which point substitution like this will need expanding. It is better to do that > now. Ok sure, will do that in patch v2. - Yash > > Andrew
diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml index a0efd8d..ab22056 100644 --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -13,7 +13,9 @@ maintainers: properties: compatible: items: - - const: sifive,fu540-c000-gpio + - enum: + - sifive,fu540-c000-gpio + - sifive,fu740-c000-gpio - const: sifive,gpio0 reg: diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt index 6b25a80..1966b2c 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt @@ -3,9 +3,11 @@ Device tree configuration for i2c-ocores Required properties: - compatible : "opencores,i2c-ocores" "aeroflexgaisler,i2cmst" - "sifive,fu540-c000-i2c", "sifive,i2c0" + "sifive,<chip>-i2c", "sifive,i2c0" For Opencore based I2C IP block reimplemented in - FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt + SiFive SoC. Supported compatible strings are: + "sifive,fu540-c000-i2c" and "sifive,fu740-c000-i2c" + Please refer to sifive-blocks-ip-versioning.txt for additional details. - reg : bus address start and address range size of device - clocks : handle to the controller clock; see the note below. diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml index 5ac2527..84e6691 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml @@ -25,12 +25,15 @@ description: properties: compatible: items: - - const: sifive,fu540-c000-pwm + - enum: + - sifive,fu540-c000-pwm + - sifive,fu740-c000-pwm - const: sifive,pwm0 description: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported - compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0 - as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the + compatible strings are "sifive,fu540-c000-pwm" and + "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the + SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the SiFive PWM v0 IP block with no chip integration tweaks. Please refer to sifive-blocks-ip-versioning.txt for details. diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6925e0..eb6843f 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -28,11 +28,17 @@ properties: - items: - enum: - sifive,rocket0 + - sifive,bullet0 - sifive,e5 + - sifive,e7 - sifive,e51 + - sifive,e71 - sifive,u54-mc + - sifive,u74-mc - sifive,u54 + - sifive,u74 - sifive,u5 + - sifive,u7 - const: riscv - const: riscv # Simulator only description: diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml index 92283f6..3ac5c7f 100644 --- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml @@ -17,7 +17,9 @@ allOf: properties: compatible: items: - - const: sifive,fu540-c000-uart + - enum: + - sifive,fu540-c000-uart + - sifive,fu740-c000-uart - const: sifive,uart0 description: diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml index 56dcf1d..6e7e394 100644 --- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml +++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml @@ -17,15 +17,17 @@ allOf: properties: compatible: items: - - const: sifive,fu540-c000-spi + - enum: + - sifive,fu540-c000-spi + - sifive,fu740-c000-spi - const: sifive,spi0 description: Should be "sifive,<chip>-spi" and "sifive,spi<version>". Supported compatible strings are - - "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated - onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive - SPI v0 IP block with no chip integration tweaks. + "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0 + as integrated onto the SiFive FU540 and FU740 chip resp, and "sifive,spi0" + for the SiFive SPI v0 IP block with no chip integration tweaks. Please refer to sifive-blocks-ip-versioning.txt for details SPI RTL that corresponds to the IP block version numbers can be found here -
Add new compatible strings to the DT binding documents to support SiFive FU740-C000. Also, add new compatible strings in cpus.yaml to support the E71 and U74 CPU cores ("harts") that are present on FU740-C000 SoC. Signed-off-by: Yash Shah <yash.shah@sifive.com> --- Documentation/devicetree/bindings/gpio/sifive,gpio.yaml | 4 +++- Documentation/devicetree/bindings/i2c/i2c-ocores.txt | 6 ++++-- Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 9 ++++++--- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ Documentation/devicetree/bindings/serial/sifive-serial.yaml | 4 +++- Documentation/devicetree/bindings/spi/spi-sifive.yaml | 10 ++++++---- 6 files changed, 28 insertions(+), 11 deletions(-)