| Message ID | 1607403341-57214-2-git-send-email-yash.shah@sifive.com |
|---|---|
| State | Accepted |
| Commit | 75e6d7248efccc2b13d0f3811b29d3e5cb04bcad |
| Headers | show |
| Series | arch: riscv: add board and SoC DT file support | expand |
On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote: > > Add new compatible strings in cpus.yaml to support the E71 and U74 CPU > cores ("harts") that are present on FU740-C000 SoC. > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Bin Meng <bin.meng@windriver.com>
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6925e0..eb6843f 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -28,11 +28,17 @@ properties: - items: - enum: - sifive,rocket0 + - sifive,bullet0 - sifive,e5 + - sifive,e7 - sifive,e51 + - sifive,e71 - sifive,u54-mc + - sifive,u74-mc - sifive,u54 + - sifive,u74 - sifive,u5 + - sifive,u7 - const: riscv - const: riscv # Simulator only description:
Add new compatible strings in cpus.yaml to support the E71 and U74 CPU cores ("harts") that are present on FU740-C000 SoC. Signed-off-by: Yash Shah <yash.shah@sifive.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+)