| Message ID | 20201217180638.22748-32-digetx@gmail.com |
|---|---|
| State | Accepted |
| Commit | 029f7e24a65df641ac843cda8dabe359ff0826eb |
| Headers | show |
| Series | Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs | expand |
On Thu, 17 Dec 2020 at 19:07, Dmitry Osipenko <digetx@gmail.com> wrote: > > The core voltage shall not drop until state of Core domain is synced, > i.e. all device drivers that use Core domain are loaded and ready. > > Support Core domain state syncing. The Core domain driver invokes the > core-regulator voltage syncing once the state of domain is synced, at > this point the Core voltage is allowed to go lower. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> This looks reasonable to me, feel free to add: Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Kind regards Uffe > --- > drivers/soc/tegra/regulators-tegra20.c | 19 ++++++++++++++++++- > drivers/soc/tegra/regulators-tegra30.c | 18 +++++++++++++++++- > 2 files changed, 35 insertions(+), 2 deletions(-) > > diff --git a/drivers/soc/tegra/regulators-tegra20.c b/drivers/soc/tegra/regulators-tegra20.c > index 367a71a3cd10..e2c11d442591 100644 > --- a/drivers/soc/tegra/regulators-tegra20.c > +++ b/drivers/soc/tegra/regulators-tegra20.c > @@ -16,6 +16,8 @@ > #include <linux/regulator/driver.h> > #include <linux/regulator/machine.h> > > +#include <soc/tegra/common.h> > + > struct tegra_regulator_coupler { > struct regulator_coupler coupler; > struct regulator_dev *core_rdev; > @@ -38,6 +40,21 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, > int core_cur_uV; > int err; > > + /* > + * Tegra20 SoC has critical DVFS-capable devices that are > + * permanently-active or active at a boot time, like EMC > + * (DRAM controller) or Display controller for example. > + * > + * The voltage of a CORE SoC power domain shall not be dropped below > + * a minimum level, which is determined by device's clock rate. > + * This means that we can't fully allow CORE voltage scaling until > + * the state of all DVFS-critical CORE devices is synced. > + */ > + if (tegra_soc_core_domain_state_synced()) { > + pr_info_once("voltage state synced\n"); > + return 0; > + } > + > if (tegra->core_min_uV > 0) > return tegra->core_min_uV; > > @@ -58,7 +75,7 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, > */ > tegra->core_min_uV = core_max_uV; > > - pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); > + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); > > return tegra->core_min_uV; > } > diff --git a/drivers/soc/tegra/regulators-tegra30.c b/drivers/soc/tegra/regulators-tegra30.c > index 0e776b20f625..42d675b79fa3 100644 > --- a/drivers/soc/tegra/regulators-tegra30.c > +++ b/drivers/soc/tegra/regulators-tegra30.c > @@ -16,6 +16,7 @@ > #include <linux/regulator/driver.h> > #include <linux/regulator/machine.h> > > +#include <soc/tegra/common.h> > #include <soc/tegra/fuse.h> > > struct tegra_regulator_coupler { > @@ -39,6 +40,21 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, > int core_cur_uV; > int err; > > + /* > + * Tegra30 SoC has critical DVFS-capable devices that are > + * permanently-active or active at a boot time, like EMC > + * (DRAM controller) or Display controller for example. > + * > + * The voltage of a CORE SoC power domain shall not be dropped below > + * a minimum level, which is determined by device's clock rate. > + * This means that we can't fully allow CORE voltage scaling until > + * the state of all DVFS-critical CORE devices is synced. > + */ > + if (tegra_soc_core_domain_state_synced()) { > + pr_info_once("voltage state synced\n"); > + return 0; > + } > + > if (tegra->core_min_uV > 0) > return tegra->core_min_uV; > > @@ -59,7 +75,7 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, > */ > tegra->core_min_uV = core_max_uV; > > - pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); > + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); > > return tegra->core_min_uV; > } > -- > 2.29.2 >
diff --git a/drivers/soc/tegra/regulators-tegra20.c b/drivers/soc/tegra/regulators-tegra20.c index 367a71a3cd10..e2c11d442591 100644 --- a/drivers/soc/tegra/regulators-tegra20.c +++ b/drivers/soc/tegra/regulators-tegra20.c @@ -16,6 +16,8 @@ #include <linux/regulator/driver.h> #include <linux/regulator/machine.h> +#include <soc/tegra/common.h> + struct tegra_regulator_coupler { struct regulator_coupler coupler; struct regulator_dev *core_rdev; @@ -38,6 +40,21 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, int core_cur_uV; int err; + /* + * Tegra20 SoC has critical DVFS-capable devices that are + * permanently-active or active at a boot time, like EMC + * (DRAM controller) or Display controller for example. + * + * The voltage of a CORE SoC power domain shall not be dropped below + * a minimum level, which is determined by device's clock rate. + * This means that we can't fully allow CORE voltage scaling until + * the state of all DVFS-critical CORE devices is synced. + */ + if (tegra_soc_core_domain_state_synced()) { + pr_info_once("voltage state synced\n"); + return 0; + } + if (tegra->core_min_uV > 0) return tegra->core_min_uV; @@ -58,7 +75,7 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, */ tegra->core_min_uV = core_max_uV; - pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); return tegra->core_min_uV; } diff --git a/drivers/soc/tegra/regulators-tegra30.c b/drivers/soc/tegra/regulators-tegra30.c index 0e776b20f625..42d675b79fa3 100644 --- a/drivers/soc/tegra/regulators-tegra30.c +++ b/drivers/soc/tegra/regulators-tegra30.c @@ -16,6 +16,7 @@ #include <linux/regulator/driver.h> #include <linux/regulator/machine.h> +#include <soc/tegra/common.h> #include <soc/tegra/fuse.h> struct tegra_regulator_coupler { @@ -39,6 +40,21 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, int core_cur_uV; int err; + /* + * Tegra30 SoC has critical DVFS-capable devices that are + * permanently-active or active at a boot time, like EMC + * (DRAM controller) or Display controller for example. + * + * The voltage of a CORE SoC power domain shall not be dropped below + * a minimum level, which is determined by device's clock rate. + * This means that we can't fully allow CORE voltage scaling until + * the state of all DVFS-critical CORE devices is synced. + */ + if (tegra_soc_core_domain_state_synced()) { + pr_info_once("voltage state synced\n"); + return 0; + } + if (tegra->core_min_uV > 0) return tegra->core_min_uV; @@ -59,7 +75,7 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, */ tegra->core_min_uV = core_max_uV; - pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); return tegra->core_min_uV; }
The core voltage shall not drop until state of Core domain is synced, i.e. all device drivers that use Core domain are loaded and ready. Support Core domain state syncing. The Core domain driver invokes the core-regulator voltage syncing once the state of domain is synced, at this point the Core voltage is allowed to go lower. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/soc/tegra/regulators-tegra20.c | 19 ++++++++++++++++++- drivers/soc/tegra/regulators-tegra30.c | 18 +++++++++++++++++- 2 files changed, 35 insertions(+), 2 deletions(-)